Min-sum based hybrid non-binary low density parity check decoder

Patent metadata

Field	Value
Publication number	US-9048874-B2
Application number	US-201313886103-A
Country	US
Kind code	B2
Filing date	May 2, 2013
Priority date	Mar 15, 2013
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.

First claim

What is claimed is:

1. An apparatus for decoding data comprising:
a variable node processor, wherein the variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages;
a check node processor, wherein the check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages, wherein the vari…

Assignees

• Lsi Corp

Inventors

• Wang Chung-Li
• Li Zongwang
• Li Shu
• Zhang Fan
• Yang Shaohua

Classifications

• H03M13/13 Primary

  Electricity · mapped topic

• H03M13/1122 Primary

  Electricity · mapped topic

• H03M13/1171

  Electricity · mapped topic

• H03M13/6583

  Electricity · mapped topic

• H03M13/1125

  Electricity · mapped topic