Generalized ldpc encoder, generalized ldpc encoding method and storage device
US-2024120945-A1 · Apr 11, 2024 · US
LDPC multi-decoder architectures
US9048871B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9048871-B2 |
| Application number | US-201414303994-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 13, 2014 |
| Priority date | Jan 14, 2011 |
| Publication date | Jun 2, 2015 |
| Grant date | Jun 2, 2015 |
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Abstract
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Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix corresponding to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check-matrix is configured to operate with nx check node processing elements (NPEs) and ny bit NPEs. The super-parity-check matrix includes a plurality of parity check matrices. Each parity check matrix is configured to operate with x check NPEs and y bit NPEs. The numbers n, x, and y, are selected such that ny codeword bits are processed in the single time unit by a high throughput decoder and y codeword bits are processed in the single time unit by a low throughput decoder.
First claim
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What is claimed is: 1. An apparatus, comprising: a super-parity-check matrix corresponding to at least a portion of a low density parity check (LDPC) code matrix, wherein the super-parity-check-matrix is configured to operate with nx check node processing elements (NPEs) and ny bit NPEs, and further wherein the super-parity-check matrix comprises a plurality of parity check matrices, wherein each parity check matrix is configured to operate with x check NPEs and y bit NPEs; and…
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Electricity · mapped topic
Electricity · mapped topic
- H03M13/1108Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9048871B2 cover?
- Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix corresponding to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check-matrix is configured to operate with nx check node processing elements (NPEs) and ny bit NPEs. The super-parity…
- Who is the assignee on this patent?
- Marvell World Trade Ltd
- What technology area does this patent fall under?
- Primary CPC classification H03M13/1108. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).