Low density parity check decoder with flexible saturation

Patent metadata

Field	Value
Publication number	US-9048870-B2
Application number	US-201313777976-A
Country	US
Kind code	B2
Filing date	Feb 26, 2013
Priority date	Nov 19, 2012
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

Embodiments of the present inventions are related to systems and methods for decoding data in an LDPC decoder with flexible saturation levels for variable node probability values.

First claim

What is claimed is:

1. An apparatus for processing data comprising:
a low density parity check decoder operable to generate decoded values for the data, comprising:
a variable node processor operable to generate variable node to check node messages and to calculate variable node values for a plurality of variable nodes in an H matrix based on check node to variable node messages;
a check node processor operable to generate the check node to variable node messages and to calculate checksums based on the variable node to check node messages; and
a saturation circuit operable to limit the variable node values of ones of the plurality of variable nodes that are marked as suspicious variable nodes.

2. The apparatus of claim 1 , wherein the low density parity check code comprises an irregular low density parity check code.

3. The apparatus of claim 2 , wherein the plurality of variable nodes comprise lower column weight variable nodes and higher column weight variable nodes, and wherein the suspicious variable nodes comprise ones of the lower column weight variable nodes likely to contain erroneous variable node values.

4. The apparatus of claim 3 , wherein the lower column weight variable nodes likely to contain erroneous variable node values comprise variable nodes for which connected check nodes have failed a number of parity checks in successive iterations.

5. The apparatus of claim 1 , wherein the saturation circuit is operable to limit log likelihood ratio values for the suspicious variable nodes to a saturation level.

6. The apparatus of claim 1 , wherein the variable node processor and the check node processor are operable to perform min-sum based low density parity check decoding.

7. The apparatus of claim 1 , wherein the saturation circuit is operable to compare the calculated variable node values to a saturation level and to replace ones of the calculated variable node values that exceed the saturation level with the saturation level.

8. The apparatus of claim 1 , further comprising a data detector operable to generate detected values for input data, wherein the detected values comprise soft probabilities, and wherein the data detector and low density parity check decoder are operable to perform global iterations to process the data.

9. The apparatus of claim 8 , wherein the saturation circuit is operable to limit the variable node values of the suspicious variable nodes to a plurality of saturation levels, and wherein the saturation circuit is operable to select from among the plurality of saturation levels based at least in part on a global iteration number.

10. The apparatus of claim 1 , wherein the variable node processor is operable to perform variable node offsetting, and wherein the saturation circuit is operable to disable the variable node offsetting for at least the suspicious variable nodes.

11. The apparatus of claim 1 , wherein the apparatus is implemented as an integrated circuit.

12. The apparatus of claim 1 , wherein the apparatus is incorporated in a storage device.

13. The apparatus of claim 12 , wherein the storage device comprises a redundant array of independent disks.

14. The apparatus of claim 1 , wherein the apparatus is incorporated in a transmission system.

15. A method for processing data in a low density parity check decoder comprising:
calculating variable node values for a plurality of variable nodes in an H matrix based on check node to variable node messages;
limiting the variable node values of suspicious variable nodes to saturation levels;
generating variable node to check node messages based on the variable node values;
performing parity check calculations based on the variable node to check node messages; and
calculating the check node to variable node messages.

16. The method of claim 15 , further comprising identifying the suspicious variable nodes as variable nodes with low column weights in an irregular low density parity check decoder and which have connected check nodes with failing parity checks for a number of iterations.

17. The method of claim 15 , wherein calculating the check node to variable node messages comprises performing min-sum based low density parity check decoding.

18. The method of claim 15 , wherein calculating the variable node values comprises calculating log likelihood ratio values, and wherein limiting the variable node values comprises replacing the log likelihood ratio values with the saturation levels for those log likelihood ratio values that exceeded the saturation levels.

19. The method of claim 15 , further comprising selecting the saturation levels based on a global iteration number.

20. A storage system comprising:
a storage medium maintaining a data set;
a read/write head assembly operable to sense the data set on the storage medium; and
a low density parity check decoder operable to generate decoded values for the data set, comprising:
a variable node processor operable to generate variable node to check node messages and to calculate variable node values for a plurality of variable nodes in an H matrix based on check node to variable node messages;
a check node processor operable to generate the check node to variable node messages and to calculate checksums based on the variable node to check node messages; and
a saturation circuit operable to limit the variable node values of ones of the plurality of variable nodes that are marked as suspicious variable nodes.

Assignees

• Lsi Corp

Inventors

• Li Shu
• Li Zongwang
• Yang Shaohua
• Zhang Fan

Classifications

• H03M13/6591

  Truncation, saturation and clamping · CPC title

• H03M13/1171

  Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes · CPC title

• H03M13/6508

  Flexibility, adaptability, parametrability and configurability of the implementation · CPC title

• H03M13/1125

  using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs · CPC title

• H03M13/6331

  Error control coding in combination with equalisation · CPC title