Integrated physical coding sublayer and forward error correction in networking applications
US-2015381312-A1 · Dec 31, 2015 · US
Shift register-based layered low density parity check decoder
US9048867B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9048867-B2 |
| Application number | US-201313898685-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 21, 2013 |
| Priority date | May 21, 2013 |
| Publication date | Jun 2, 2015 |
| Grant date | Jun 2, 2015 |
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Abstract
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An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus for layered low density parity check decoding comprising: a variable node processor operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages; and a check node processor comprising an intermediate message generator circuit operable to generate intermediate check node messages comprising a minimum, a next minimum and an index of minimum value in the variable no…
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Electricity · mapped topic
- H03M13/1105Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H03M13/1117Primary
Electricity · mapped topic
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- What does patent US9048867B2 cover?
- An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate int…
- Who is the assignee on this patent?
- Lsi Corp
- What technology area does this patent fall under?
- Primary CPC classification H03M13/1105. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).