Digital to analog converter with current steering source for reduced glitch energy error

US9048864B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9048864-B2
Application numberUS-201414218100-A
CountryUS
Kind codeB2
Filing dateMar 18, 2014
Priority dateJan 16, 2013
Publication dateJun 2, 2015
Grant dateJun 2, 2015

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  5. First independent claim

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Abstract

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A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the first control node and a first current output node or between the second control node and a second current output node, and an activation current source provides activation current to the buffer circuit via the first and second control nodes. The master replica bias network replicates biasing of the buffer circuit relative to a replica control node and drives the buffer circuit to maintain the first control node, the second control node and the replica control node at a common master control voltage.

First claim

Opening claim text (preview).

The invention claimed is: 1. A digital to analog converter, comprising: a switch circuit operative to steer a source current from a source node to a selected one of first and second control nodes based on a data bit; a buffer circuit that buffers said source current between said first control node and a first current output node and between said second control node and a second current output node; an activation current source that is configured to provide an activation curren…

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What does patent US9048864B2 cover?
A digital to analog converter including a current steering source and a master replica bias network. The current steering source includes a data current source providing a source current to a source node, a switch circuit operative to steer the source current to a selected one of first and second control nodes based on a data bit, a buffer circuit that buffers the source current between the fir…
Who is the assignee on this patent?
Freescale Semiconductor Inc
What technology area does this patent fall under?
Primary CPC classification H03M1/0863. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).