Method and apparatus for parallel data interfacing using combined coding and recording medium therefor

Patent metadata

Field	Value
Publication number	US-9048855-B2
Application number	US-201314047377-A
Country	US
Kind code	B2
Filing date	Oct 7, 2013
Priority date	May 27, 2006
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

A semiconductor device may include a coding lookup table unit including a plurality of coding lookup tables each of which is selected by a respectively selection signal, and a selection unit configured to receive one of N-bit parallel data and extract respective encoded data corresponding to the selection signal and to which the N-bit parallel data is mapped from the coding lookup table unit, and encoded data and extract respective N-bit parallel data corresponding to the selection signal and to which the encoded data is mapped from the coding lookup table unit, wherein N is 2 or an integer greater than 2, and wherein the coding lookup tables respectively store a plurality of coded data patterns that respectively correspond to patterns of the N-bit parallel data and are random temporally and spatially.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a scrambling code generator configured to generate a scrambling code using a seed;
a scrambler configured to scramble a first parallel data group, which includes at least two sets of N-bit parallel data, using the scrambling code and generate a second parallel data group, which includes at least two sets of N-bit scrambled parallel data, where N is 2 or an integer greater than 2;
a balance encoding block configured to receive the second parallel data group, perform direct current (DC) balance encoding of the N-bit scrambled parallel data sets in the second parallel data group, and generate M-bit balance codes, where M is an integer greater than N; and
an output driver configured to sequentially output the balance codes and the seed through a plurality of data lines.

2. The semiconductor device as claimed in claim 1 , wherein the balance encoding block selectively inverts the N-bit scrambled parallel data sets according to the number of bits having a first logic level or a second logic level in each of the N-bit scrambled parallel data sets and adds a flag signal indicating inversion or non-inversion to each of the N-bit scrambled parallel data sets.

3. The semiconductor device as claimed in claim 1 , wherein the scrambler comprises a logical operator configured to perform an exclusive OR operation on bits in the first parallel data group and bits in the scrambling code one on one.

4. The semiconductor device as claimed in claim 1 , wherein the output driver is configured to sequentially output the balance codes one by one through the plurality of data lines before outputting the seed through the plurality of data lines.

5. A semiconductor device, comprising:
a data receiver configured to receive M-bit balance codes, each of which is obtained by direct current (DC) balance encoding each sets of N-bit scrambled parallel data in a second parallel data group generated by scrambling a first parallel data group comprising at least two sets of N-bit parallel data, and a seed through a plurality of data lines, where M is 2 or an integer greater than 2 and N is an integer lesser than M;
a descrambling code generator configured to generate a descrambling code using the seed;
a balance decoding block configured to perform DC balance decoding of the balance codes and extract the second parallel data group comprising the at least two sets of N-bit scrambled parallel data; and
a descrambler configured to descramble the second parallel data group extracted by the balance decoding block using the descrambling code and extract the first parallel data group.

6. The semiconductor device as claimed in claim 5 , wherein the balance decoding block selectively inverts the balance codes according to a predetermined flag signal included in each of the balance codes.

7. The semiconductor device as claimed in claim 5 , wherein the descrambler comprises a logical operator configured to perform an exclusive OR operation on bits in the second parallel data group and bits in the descrambling code one on one.

8. The semiconductor device as claimed in claim 5 , wherein the data receiver sequentially receives the balance codes one by one through the plurality of data lines and then receives the seed through the plurality of data lines.

Assignees

• Samsung Electronics Co Ltd
• Samsung Electronics Co Ltd

Inventors

• Bae Seung Jun
• Ahn Jong Keun
• Choe Kwang Chol

Classifications

• H03K19/00346 Primary

  Modifications for eliminating interference or parasitic voltages or currents · CPC title

• H03M5/00 Primary

  Conversion of the form of the representation of individual digits · CPC title

• H04L25/4908

  using mBnB codes · CPC title

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H04L25/03866

  using scrambling · CPC title