Frequency locked loop circuit
US-2024106443-A1 · Mar 28, 2024 · US
Apparatus and methods for synchronizing phase-locked loops
US9048847B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9048847-B2 |
| Application number | US-201314034917-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 24, 2013 |
| Priority date | Sep 24, 2013 |
| Publication date | Jun 2, 2015 |
| Grant date | Jun 2, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's division value. The reset phase adjustment calculator can include a counter for counting a number of cycles of the reference clock signal since initialization of the fractional-N synthesizer, and the reset phase adjustment calculator can generate a phase adjustment signal based on the count. The synchronization circuit can synchronize the PLL in response to a synchronization signal, and can correct for a synchronization phase error indicated by the phase adjustment signal.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus comprising: a first phase-locked loop (PLL) configured to receive a reference clock signal and to generate an output clock signal, wherein the first PLL comprises a programmable divider configured to receive a division signal, wherein a ratio of a frequency of the output clock signal to a frequency of the reference clock signal changes in relation to the division signal; a first control circuit configured to generate the division signal, where…
Assignees
Inventors
Classifications
- H03L7/085Primary
Electricity · mapped topic
- H03L7/1976Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9048847B2 cover?
- Apparatus and methods for synchronizing phase-locked loops (PLLs) are provided. In certain implementations, a fractional-N synthesizer includes a PLL and a control circuit that controls a division value of the PLL. The control circuit includes an interpolator, a reset phase adjustment calculator, and a synchronization circuit. The interpolator can control a fractional portion of the PLL's divis…
- Who is the assignee on this patent?
- Analog Devices Technology, Analog Devices Global
- What technology area does this patent fall under?
- Primary CPC classification H03L7/085. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).