Sealed crystal oscillator and semiconductor package including the same

Patent metadata

Field	Value
Publication number	US-9048808-B2
Application number	US-201313803308-A
Country	US
Kind code	B2
Filing date	Mar 14, 2013
Priority date	Feb 21, 2013
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

A semiconductor package includes a package substrate; an integrated circuit chip formed on one surface of the package substrate; and a sealed quartz oscillator formed on at least one of an inside, one surface, and the other surface of the package substrate, wherein the sealed quartz oscillator includes a substrate, a quartz blank formed on one surface of the substrate, and a sealing cap covering at least one surface of the quartz blank and including metal.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate;
an integrated circuit chip disposed on one surface of the package substrate; and
a sealed quartz oscillator disposed on at least one of an interior portion and a first exterior surface of the package substrate,
wherein the sealed quartz oscillator includes a substrate, a quartz blank disposed on one surface of the substrate, and a sealing cap covering at least one surface of the quartz blank, wherein the sealing cap comprises metal,
wherein the sealed quartz oscillator further comprises a plurality of electrode patterns electrically connected to the quartz blank disposed on the substrate, and a plurality of through-electrodes electrically connected to the plurality of electrode patterns disposed through the substrate, respectively, and
wherein at least one of the plurality of through-electrodes is positioned on a side surface or an upper surface of the quartz blank.

2. The semiconductor package of claim 1 , wherein the sealing cap covers an upper surface or a side surface of the quartz blank.

3. The semiconductor package of claim 2 , wherein the substrate is in a line-shape, and the sealing cap is formed on the substrate in a box-shape to cover the quartz blank.

4. The semiconductor package of claim 2 , wherein the substrate is in a L-shape, and the sealing cap is formed on the substrate in an L-shape opposite to the L-shape of the substrate to cover the quartz blank.

5. The semiconductor package of claim 2 , wherein the substrate is in a U-shape, and the sealing cap is formed on the substrate in a line-shape to cover the quartz blank.

6. The semiconductor package of claim 1 , wherein the sealed quartz oscillator is formed on a side surface, an upper surface, or a lower surface of the integrated circuit chip.

7. The semiconductor package of claim 1 , wherein the substrate and the sealing cap are bonded together by a bonding portion that is formed through melting of a metal material.

8. The semiconductor package of claim 7 , wherein the metal material is AuSn.

9. The semiconductor package of claim 1 , wherein the semiconductor package is in a POP (Package On Package) shape.

10. The semiconductor package of claim 1 , wherein the integrated circuit chip comprises a plurality of stacked integrated circuit chips.

Assignees

• Park Jae-Jin
• Lee Hee-Seok
• Hyun Ji-Hwan
• Choo Kang-Yeop
• Samsung Electronics Co Ltd

Inventors

• Park Jae-Jin
• Lee Hee-Seok
• Hyun Ji-Hwan
• Choo Kang-Yeop

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title