Apparatus and methods for buffer linearization

Patent metadata

Field	Value
Publication number	US-9048801-B2
Application number	US-201414337944-A
Country	US
Kind code	B2
Filing date	Jul 22, 2014
Priority date	Mar 4, 2013
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

Apparatus and methods for buffer linearization are provided. In certain implementations, an amplifier includes a buffer circuit and a gain circuit. The buffer circuit includes a buffer transistor pair used to buffer a differential input signal to generate a differential buffered signal. Additionally, the gain circuit includes a gain transistor pair configured to amplify the buffered differential signal to generate an amplified differential signal. The buffer circuit can include a linearization transistor pair configured to decrease the buffer circuit's output impedance and to provide feedback that reduces changes in the voltage of the differential buffered signal in response to displacement currents associated with the C JC or C GD capacitances of the gain transistor pair.

First claim

What is claimed is:

1. An apparatus comprising:
a gain circuit comprising a first gain transistor and a second gain transistor, wherein a source of the first gain transistor is electrically connected to a source of the second gain transistor, and wherein the first and second gain transistors have a first type of device polarity; and
a buffer circuit comprising:
a first buffer transistor comprising a source electrically connected to a gate of the first gain transistor and a gate…

Assignees

• Analog Devices Inc

Inventors

• Foroudi Omid

Classifications

• H03F3/19 Primary

  Electricity · mapped topic

• H03G3/3036 Primary

  Electricity · mapped topic

• H03F2200/451

  Electricity · mapped topic

• H03F3/45

  Electricity · mapped topic

• H03F2203/45722

  Electricity · mapped topic