Semiconductor devices including avalanche photodetector diodes integrated on waveguides and methods for fabricating the same

Patent metadata

Field	Value
Publication number	US-9048371-B2
Application number	US-201314045180-A
Country	US
Kind code	B2
Filing date	Oct 3, 2013
Priority date	Oct 3, 2013
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a method for fabricating a semiconductor device includes etching a trench into a waveguide layer in a detector region of a semiconductor substrate. An avalanche photodetector diode is formed about the trench. Forming the avalanche photodetector diode includes forming a multiplication region in the waveguide layer laterally adjacent to the trench. An absorption region is formed at least partially disposed in the trench.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, the method comprising:
etching a trench into a waveguide layer in a detector region of a semiconductor substrate, wherein etching the trench into the waveguide layer comprises removing material from the waveguide layer to expose a sidewall and a lower section of the waveguide layer to form the trench; and
forming an avalanche photodetector diode about the trench comprising:
forming a first multiplication region in the waveguide layer laterally adjacent to the trench, wherein forming the avalanche photodetector diode comprises P− doping the sidewall and the lower section to form a P− charge layer, and wherein forming the first multiplication region comprises forming the first multiplication region laterally adjacent to the P− charge layer; and
forming an absorption region at least partially disposed in the trench, wherein forming the first multiplication region comprises forming an n-well in the waveguide layer laterally spaced apart from the P− charge layer to form the first multiplication region disposed between the n-well and the P− charge layer.

2. The method of claim 1 , wherein forming the avalanche photodetector diode comprises forming a second multiplication region in the waveguide layer laterally adjacent to the trench, wherein the absorption region is disposed between the first and second multiplication regions.

3. The method of claim 1 , wherein etching the trench into the waveguide layer comprises removing material from the waveguide layer for a depth of from about 1.25 to about 2.75 μm to form the trench.

4. The method of claim 1 , wherein etching the trench into the waveguide layer comprises etching the trench into the waveguide layer using a wet etching process.

5. The method of claim 1 , wherein forming the first multiplication region comprises forming the first multiplication region having a width defined between the n-well and the P− charge layer of from about 0.3 to about 1.5 μm.

6. The method of claim 1 , wherein forming the avalanche photodetector diode comprises implanting an N+ dopant into a first upper portion of the n-well for forming an N+ electrode.

7. The method of claim 6 , wherein forming the avalanche photodetector diode comprises activating the N+ dopant using an annealing process to form the N+ electrode.

8. The method of claim 6 , wherein forming the avalanche photodetector diode comprises forming an P+ electrode along a second upper portion of the absorption region.

9. The method of claim 8 , wherein forming the avalanche photodetector diode comprises forming a first metal silicide region in the N+ electrode and a second metal silicide region in the P+ electrode.

10. The method of claim 9 , further comprising:
depositing an ILD layer of dielectric material overlying the avalanche photodetector diode; and
forming a first contact and a second contact extending through the ILD layer to the first and second metal silicide regions, respectively.

11. The method of claim 1 , wherein forming the absorption region comprises filling the trench with germanium (Ge) using an epitaxial growth process.

12. A method for fabricating a semiconductor device, the method comprising:
forming a first field oxide layer section and a second field oxide layer section overlying a waveguide layer in a detector region of a semiconductor substrate, wherein the first and second field oxide layer sections are spaced apart to expose an intermediate section of the waveguide layer;
etching a trench into the intermediate section of the waveguide layer to form a recessed waveguide layer section having sidewalls and a lower section extending between the sidewalls;
P− doping the sidewalls and the lower section to form a P− charge layer in the recessed waveguide layer section;
forming a first n-well in the waveguide layer underlying the first field oxide layer section and laterally spaced apart from the P− charge layer to form a first multiplication region in the waveguide layer disposed between the first n-well and the P− charge layer;
forming a second n-well in the waveguide layer underlying the second field oxide layer section and laterally spaced apart from the P− charge layer to form a second multiplication region in the waveguide layer disposed between the second n-well and the P− charge layer;
N+ doping upper portions of the first and second n-wells for forming first and second N+ electrodes, respectively;
depositing germanium (Ge) into the trench overlying the P− charge layer to form an absorption region; and
forming a P+ electrode along an upper portion of the absorption region.

13. The method of claim 12 , wherein etching the trench into the intermediate section comprises forming the recessed waveguide layer section having a thickness of from about 0.25 to about 0.75 μm.

14. The method of claim 12 , further comprising:
forming a silicon (Si) cap overlying the absorption region.

15. The method of claim 14 , wherein forming the P+ electrode comprises P+ doping the Si cap and the upper portion of the absorption region.

16. The method of claim 12 , wherein N+ doping the upper portions of the first and second n-wells comprises implanting an N+ dopant through the first and second field oxide layer sections into the upper portions of the first and second n-wells for forming the first and second N+ electrodes, respectively.

17. The method of claim 12 , wherein P− doping the sidewalls and the lower section comprises angle implanting a P− dopant into the sidewalls and the lower section.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Ang Kah-Wee
• Verma Purakh Raj

Classifications

• H10F77/413

  directly associated or integrated with the devices, e.g. back reflectors (directly associated or integrated with photovoltaic cells H10F77/42) · CPC title

• H10F71/121

  The active layers comprising only Group IV materials · CPC title

• H10F30/2255 Primary

  in which the active layers form heterostructures, e.g. SAM structures · CPC title

• H01L31/02327

  Electricity · mapped topic

• H01L31/1075 Primary

  Electricity · mapped topic