Semiconductor device and manufacturing method thereof

US9048321B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9048321-B2
Application numberUS-201213686332-A
CountryUS
Kind codeB2
Filing dateNov 27, 2012
Priority dateDec 2, 2011
Publication dateJun 2, 2015
Grant dateJun 2, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall insulating layer is provided to cover a side surface of the first sidewall insulating layer. The first sidewall insulating layer is an aluminum oxide film in which a crevice with an even shape is formed on its side surface. The second sidewall insulating layer is provided to cover the crevice. A source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film and the second sidewall insulating layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: an oxide insulating film over a substrate; an oxide semiconductor layer over the oxide insulating film; a gate insulating film over the oxide semiconductor layer; a gate electrode layer over the oxide semiconductor layer with the gate insulating film therebetween; a first sidewall insulating layer over the gate insulating film to cover a first portion of a top surface of the gate insulating film and a second portion…

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What does patent US9048321B2 cover?
Provided is a miniaturized transistor with stable and high electrical characteristics with high yield. In a semiconductor device including the transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer are stacked in this order, a first sidewall insulating layer is provided in contact with a side surface of the gate electrode layer, and a second sidewall…
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10D30/6704. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).