Display device

US9048147B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9048147-B2
Application numberUS-201213613811-A
CountryUS
Kind codeB2
Filing dateSep 13, 2012
Priority dateSep 30, 2008
Publication dateJun 2, 2015
Grant dateJun 2, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device of which frame can be narrowed and of which display characteristics are excellent is provided. In a display device including a switch portion or a buffer portion, a logic circuit portion, and a pixel portion, the pixel portion includes a first inverted staggered TFT and a pixel electrode which is connected to a wiring of the first inverted staggered TFT, the switch portion or the buffer portion includes a second inverted staggered TFT in which a first insulating layer, a semiconductor layer, and a second insulating layer are interposed between a first gate electrode and a second gate electrode, the logic circuit portion includes an inverter circuit including a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor, and the first to the fourth inverted staggered thin film transistors have the same polarity. The inverter circuit may be an EDMOS circuit.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a transistor comprising: a gate wiring over a first region of a substrate; a semiconductor layer over the gate wiring with an insulating layer interposed therebetween; a first wiring over and electrically connected to the semiconductor layer; and a second wiring over and electrically connected to the semiconductor layer; a terminal portion comprising: a first metal layer over a second region of the substrate;…

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Frequently asked questions

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What does patent US9048147B2 cover?
A display device of which frame can be narrowed and of which display characteristics are excellent is provided. In a display device including a switch portion or a buffer portion, a logic circuit portion, and a pixel portion, the pixel portion includes a first inverted staggered TFT and a pixel electrode which is connected to a wiring of the first inverted staggered TFT, the switch portion or t…
Who is the assignee on this patent?
Yamazaki Shunpei, Osada Takeshi, Miyairi Hidekazu, and 2 more
What technology area does this patent fall under?
Primary CPC classification G02F1/1368. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).