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US9048136B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9048136-B2 |
| Application number | US-201113282261-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 26, 2011 |
| Priority date | Oct 26, 2011 |
| Publication date | Jun 2, 2015 |
| Grant date | Jun 2, 2015 |
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Abstract
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A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.
First claim
Opening claim text (preview).
What is claimed is: 1. A static random access memory cell formed in a silicon layer over an insulating layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node, comprising: each of the pull-down transistors of the first and second inverters being formed in a silicon layer and over first regions below the insulating layer, the first regions having a first doping level forming first backgates for the…
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Classifications
- H10D86/201Primary
Electricity · mapped topic
Physics · mapped topic
Physics · mapped topic
Electricity · mapped topic
- H01L27/1108Primary
Electricity · mapped topic
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- What does patent US9048136B2 cover?
- A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a firs…
- Who is the assignee on this patent?
- Mann Randy W, Luning Scott D, Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10D86/201. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).