Superjunction transistor with implantation barrier at the bottom of a trench

Patent metadata

Field	Value
Publication number	US-9048115-B2
Application number	US-201213661935-A
Country	US
Kind code	B2
Filing date	Oct 26, 2012
Priority date	Oct 26, 2012
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
growing an epitaxial layer on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type;
forming a trench in the epitaxial layer;
forming a barrier region at a bottom of the trench, wherein the trench has an aspect ratio in a range of 1/12 to 1/8;
forming a doped region of a second conductivity type in the epitaxial layer and surrounding sidewalls of the trench…

Assignees

• Vanguard Int Semiconduct Corp

Inventors

• Lee Tsung-Hsiung
• Tu Shang-Hui
• Sheu Gene
• Agarwal Neelam
• Nidhi Karuna
• Lee Chia-Hao
• Sihombing Rudy Octavius

Classifications

• H10P30/222

  Electricity · mapped topic

• H10D64/2527

  Electricity · mapped topic

• H10D62/058

  Electricity · mapped topic

• H10D62/111

  Electricity · mapped topic

• H10D30/66 Primary

  Electricity · mapped topic