Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Integrated voltage regulator with embedded passive device(s) for a stacked IC
US9048112B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9048112-B2 |
| Application number | US-82593710-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 29, 2010 |
| Priority date | Jun 29, 2010 |
| Publication date | Jun 2, 2015 |
| Grant date | Jun 2, 2015 |
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- Title
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Abstract
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A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.
First claim
Opening claim text (preview).
What is claimed is: 1. A stacked semiconductor integrated circuit (IC) package, comprising: a first active circuitry of a semiconductor IC configured to receive a regulated voltage from a voltage regulator; an input/output area including a first set of through substrate vias, wherein the first set of through substrate vias are configured to enable-communication between circuitry on a different semiconductor IC and a packaging substrate coupled to the semiconductor IC; wherein…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9048112B2 cover?
- A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an i…
- Who is the assignee on this patent?
- Pan Yuancheng Christopher, Sweeney Fifin, Chua-Eoan Lew G, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10W70/685. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).