Display device and driving method and electronic apparatus of the display device

US9047809B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9047809-B2
Application numberUS-78128010-A
CountryUS
Kind codeB2
Filing dateMay 17, 2010
Priority dateApr 14, 2005
Publication dateJun 2, 2015
Grant dateJun 2, 2015

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Abstract

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To reduce a pseudo contour which occurs when displaying by a time gray scale method. When gradation is expressed with an n bit, bits each of which is shown by a binary of the gray scales are divided into three bit groups, and one frame is divided into two subframe groups. Then, a (0<a<n) subframes corresponding to bits belonging to a first bit group are divided into three or more, each about half of which is arranged in each subframe group; b (0<b<n) subframes corresponding to bits belonging to a second bit group are divided into two, each one of which is arranged in each the subframe group; and c (0≦c<n and a+b+c=n) subframes corresponding to bits belonging to a third bit group are arranged in at least one of the subframe groups. And then, an overlapped time gray scale method is applied in each subframe group to express gradation.

First claim

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What is claimed is: 1. A driving method of a display device for expressing gradation by dividing one frame into a plurality of subframes, in the case where gradation is expressed with an n bit (here n is an integer), the display device comprising: a pixel portion comprising pixels over a substrate, each of the pixels comprising a capacitor and a bottom-gate transistor comprising a compound semiconductor; a memory; and a circuit configured to output signals to the substrate by…

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What does patent US9047809B2 cover?
To reduce a pseudo contour which occurs when displaying by a time gray scale method. When gradation is expressed with an n bit, bits each of which is shown by a binary of the gray scales are divided into three bit groups, and one frame is divided into two subframe groups. Then, a (0<a<n) subframes corresponding to bits belonging to a first bit group are divided into three or more, each about ha…
Who is the assignee on this patent?
Kimura Hajime, Shishido Hideaki, Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification G09G3/32. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 02 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).