Data processing array interface having interface tiles with multiple direct memory access circuits
US-12164451-B2 · Dec 10, 2024 · US
US9047273B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9047273-B2 |
| Application number | US-201414245083-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 4, 2014 |
| Priority date | Jul 6, 2009 |
| Publication date | Jun 2, 2015 |
| Grant date | Jun 2, 2015 |
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Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described.
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What is claimed is: 1. A device comprising: a first module to monitor a data transfer between a host and a memory; a second module to assess the data transfer to provide at least one of a first assessment result and a second assessment result; and a third module to adjust a number of storage units allocated to service an additional data transfer between the host and the memory based at least in part on at least one of the first assessment result and the second assessment resul…
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