Adaptive power control of memory map storage devices

Patent metadata

Field	Value
Publication number	US-9047172-B2
Application number	US-201213688546-A
Country	US
Kind code	B2
Filing date	Nov 29, 2012
Priority date	Nov 29, 2012
Publication date	Jun 2, 2015
Grant date	Jun 2, 2015

Abstract

An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.

First claim

The invention claimed is:

1. An apparatus comprising:
a set of dynamically powered volatile memory devices to store address mapping information correlating logical addresses of received access requests to corresponding physical addresses of a storage resource to which the access requests pertain;
control logic configured to:
receive mode setting information; and
adaptively control power settings of the volatile memory devices depending on the mode setting information.

2. The apparatus as in claim 1 , wherein the storage resource is a solid state drive including multiple non-volatile memory devices to store the data; and
wherein the address mapping information stored in the volatile memory devices includes a mapping of the logical addresses to corresponding physical address of the multiple non-volatile memory devices.

3. The apparatus as in claim 2 , wherein at least a portion of the multiple non-volatile memory devices in the solid state drive is allocated to store an original copy of the address mapping information; and
wherein the dynamically powered volatile memory devices at least temporarily store at least a portion of a copy of the address mapping information stored in the portion of the multiple non-volatile memory devices.

4. The apparatus as in claim 3 , wherein the multiple non-volatile memory devices in the solid-state drive are flash memory devices.

5. The apparatus as in claim 1 , wherein the control logic, as specified by first received mode setting information, is configured to power all of the multiple volatile memory devices for storage of a first amount of address mapping information; and
wherein the control logic, as specified by second received mode setting information to reduce power consumption with respect to the first mode setting information, is configured to depower at least one but fewer than all of the multiple volatile memory devices in the set for storage of a second amount of address mapping information, the second amount of address mapping information less than the first amount of address mapping information.

6. The apparatus as in claim 1 , wherein the control logic, based on first received mode setting information indicating to operate in a reduced power consumption mode, depowers at least one but fewer than all of the multiple volatile memory devices for storage of a first amount of address mapping information; and
wherein the control logic, based on second received mode setting information, powers substantially all of the multiple volatile memory devices for storage of a second amount of address mapping information, the second amount of address mapping information greater than the first amount of address mapping information.

7. The apparatus as in claim 1 further comprising:
at least one host processor device from which to receive the access requests to the storage resource; and
an access controller configured to receive the access requests from the at least one host processor device, the access controller utilizing the address mapping information in the set of dynamically powered volatile memory devices to convert logical addresses associated with received access requests to corresponding physical addresses of the storage resource to which the access requests pertain.

8. The apparatus as in claim 1 , wherein the control logic is configured to control retrieval and storage of the address mapping information in the multiple volatile memory devices depending at least in part on the received mode setting information.

9. The apparatus as in claim 8 , wherein the control logic is configured to set at least one of the multiple volatile memory devices to operate in a paging mode during a first power mode in which fewer than all but at least one of the volatile memory devices is powered to store the address mapping information; and
wherein the control logic is configured to set the multiple volatile memory devices to operate in a non-paging mode during a second power mode in which all of the volatile memory devices are powered to store the address mapping information.

10. The apparatus as in claim 1 , wherein the control logic is configured to set at least one of the multiple volatile memory devices in a standby mode to reduce power consumption of the at least one volatile memory device in response to occurrence of a condition in which address mapping information stored in the at least one volatile memory device has not been accessed for a threshold amount of time.

11. The apparatus as in claim 1 , wherein the adaptive control of the power settings changes a capacity of available memory in the volatile memory devices to store the address mapping information.

12. The apparatus as in claim 1 , wherein the control logic, as specified by first received mode setting information, powers a first portion of the multiple volatile memory devices for storage of up to a first amount of address mapping information; and
wherein the control logic, as specified by second received mode setting information, powers a second portion of the multiple volatile memory devices for storage of a second amount of address mapping information;
wherein the second portion is greater than the first portion; and
wherein the second amount of address mapping information is greater than the first amount of address mapping information.

13. The apparatus as in claim 1 , wherein the control logic dynamically adjusts how many of the volatile memory devices are powered depending on availability of power.

14. The apparatus as in claim 13 , wherein the control logic is configured to initiate powering of an additional one of the volatile memory devices in the set in response to detecting an increase in an availability of power to power the volatile memory devices.

15. The apparatus as in claim 13 , wherein the control logic is configured to initiate depowering of at least one currently powered volatile memory device in the set in response to detecting a decrease in an availability of power to power the volatile memory devices.

16. A computer system including the apparatus in claim 1 , the computer system further comprising:
a display screen on which to render an image based at least in part on the data stored in the storage resource.

17. The computer system as in claim 16 , wherein the storage resource is a solid state drive to which the computer system has access through an access controller, the access controller utilizing the address mapping information to convert the logical addresses a associated with the access requests to the corresponding physical addresses of the solid state drive to which the access requests pertain.

18. A method comprising:
initiating storage of a portion of logical-to-physical address mapping information in a set multiple volatile memory devices including at least one powered volatile memory storage device, the logical-to-physical address mapping information correlating logical addresses of access requests to physical addresses of a storage resource to which the access requests pertain;
receiving mode setting information; and
adaptively powering the set of multiple volatile memory devices in accordance with the mode setting information.

19. The method as in claim 18 , wherein adaptively powering the set of volatile memory devices varies an amount of storage space that is available to store the portion of logical-to-physical address mapping information.

20. The method as in claim 18 further comprising:
accessing a full copy of the logical-to-physical address mapping information in a n

Assignees

• Intel Corp

Inventors

• Burke Nathaniel G
• Trika Sanjeev N

Classifications

• G06F12/02 Primary

  Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F1/32

  Means for saving power · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title