Method and system for efficient emulation of multiprocessor memory consistency

Patent metadata

Field	Value
Publication number	US-9043194-B2
Application number	US-24443402-A
Country	US
Kind code	B2
Filing date	Sep 17, 2002
Priority date	Sep 17, 2002
Publication date	May 26, 2015
Grant date	May 26, 2015

Abstract

A method (and system) of emulation in a multiprocessor system, includes performing an emulation in which a host multiprocessing system of the multiprocessor system supports a weak consistency model, and the target multiprocessing system of the multiprocessor system supports a strong consistency model.

First claim

What is claimed is:

1. A method of emulation in a multiprocessor system, said method comprising:
receiving, on a processor of a host multiprocessor system, an instruction to be emulated of a target multiprocessor system, said host multiprocessor system having a memory barrier (mbar) instruction that guarantees that all results of all memory operations before executing said mbar instruction have been registered by all processors in said host multiprocessor system before registering any results of any later instructions;
determining whether execution of said mbar instruction is required for said received instruction to be emulated before said received instruction is emulated; and
selectively executing said mbar instruction, based on said determining,
said selectively executing of said mbar instruction thereby permitting performing an emulation that is efficient, even in a condition in which the host multiprocessing system of said multiprocessor system supports a weak consistency model and the target multiprocessing system of the multiprocessor system supports a strong consistency model, by reason that said mbar instruction is executed for said received instruction only if said determining determines that said execution of said mbar instruction is necessary for emulating said received instruction.

2. The method of claim 1 , said determining comprising:
determining a sharing status of a page, said determining comprising:
determining whether a look-aside mask in a lookup table has more than one bit set;
if it is determined that the look-aside mask has more than one bit set, then determining whether a read/write mask field in the lookup table has any bits set;
if it is determined that the read/write mask has any bits set, then setting the status to a “shared write”; and
if it is determined that the read/write mask does not have any bits set, then setting the status to a “shared read”.

3. The method of claim 2 , wherein said determining a sharing status of a page further comprises:
if it is determined that the look-aside mask does not have more than one bit set, then determining whether the read/write mask has any bits set; and
if it is determined that the read/write mask has bits set, then setting the status to an “exclusive write”.

4. The method of claim 2 , where said determining a sharing status of a page further comprises:
if it is determined that the read/write mask does not have any bits set, then setting the status to an “exclusive read”.

5. The method of claim 1 , further comprising:
providing a table maintained with sharing information about locations currently being referenced.

6. The method of claim 5 , wherein said table includes a look-aside mask field and a read/write mask field, and includes information on whether a page is accessed by a processor in a read mode or in a write mode.

7. The method of claim 6 , further comprising:
when a page is brought into the system, determining what state the page has,
wherein when the page has a shared write state, then such a state is flagged.

8. The method of claim 6 , wherein said table comprises a lookup table, said method further comprising:
determining a sharing status of a page, said determining comprising:
determining whether said look-aside mask in said lookup table has more than one bit set;
if it is determined that the look-aside mask has more than one bit set, then determining whether a read/write mask field in the table has any bits set;
if it is determined that the read/write mask has any bits set, then setting the status to a “shared write”; and
if it is determined that the read/write mask does not have any bits set, then setting the status to a “shared read”.

9. The method of claim 8 , wherein said determining a sharing status of a page further comprises:
if it is determined that the look-aside mask does not have more than one bit set, then determining whether the read/write mask has any bits set;
if it is determined that the read/write mask has bits set, then setting the status to an “exclusive write”;
if it is determined that the read/write mask does not have any bits set, then setting the status to an “exclusive read”; and
ensuring a sequential consistency when instructions are emulated one at a time.

10. In a multiprocessor computing system, as executing an emulator for emulating a behavior of a target multiprocessor computing system, a method for emulating a memory consistency behavior of the target multiprocessor computing system, said method comprising:
selectively executing, prior to a memory action, a memory barrier instruction,
the memory barrier instruction ensuring that results of memory actions performed before execution of the memory barrier instruction have been obtained by all processors in a host computing system,
wherein said host computing system of said multiprocessor computing system initially determines whether said execution of said memory barrier instruction is necessary to ensure a consistency of results of said memory action, thereby ensuring an emulation that is efficient in even a worst-case emulation scenario in which said host computing system supports a weak consistency model and the target multiprocessor system of the multiprocessor computing system supports a strong consistency model, by reason that said mbar instruction is executed for an instruction received for emulation only if said determining results in determining that said mbar instruction execution is determined to be necessary for said received instruction.

11. The method of claim 10 , wherein the memory barrier instruction executed prior to a memory action is executed immediately following access to a memory location identified as having a particular state.

12. The method of claim 11 , wherein said particular state comprises a shared write state.

13. The method of claim 10 , further including:
ensuring memory consistency, if instructions in a group of instructions from the target multiprocessor computing system are reordered when translated to the host.

14. A method for efficient emulation of multiprocessor memory consistency, said method comprising:
providing a memory barrier instruction which ensures that memory actions that have been performed before execution of the memory barrier instruction have been registered by all of the processors in a host computing system of a multiprocessor system; and
selectively executing said memory barrier instruction when said multiprocessor host computing system emulates an instruction of a target multiprocessor system, as based upon a determining of whether execution of said memory barrier instruction is necessary for each received instruction being emulated,
wherein the selective execution of the memory barrier instruction provides an emulation that is efficient even in a worst-case condition in which said host computing system supports a relaxed consistency model and said target multiprocessor system specifies a strong consistency model, by reason that said memory barrier instruction is executed only when determined necessary for said received instruction by said determining.

15. The method of claim 14 , wherein the host computing system supports said relaxed consistency model with memory coherence.

16. The method of claim 14 , wherein the memory barrier instruction guarantees that all memory operations after the barrier instruction are performed after all memory operations before the barrier instruction as registered by all processors.

17. The method of claim 14 , further comprising:
providing a table maintained with sharing information ab

Assignees

• Nair Ravi
• O'Brien John Kevin
• O'Brien Kathryn Mary
• Oden Peter Howland
• Prener Daniel Arthur
• IBM

Inventors

• Nair Ravi
• O'Brien John Kevin
• O'Brien Kathryn Mary
• Oden Peter Howland
• Prener Daniel Arthur

Classifications

• G06F12/1072 Primary

  Decentralised address translation, e.g. in distributed shared memory systems · CPC title

• G06F2212/682

  Multiprocessor TLB consistency · CPC title

• G06F2212/656

  Address space sharing · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title