Memory device

Patent metadata

Field	Value
Publication number	US-9042161-B2
Application number	US-201113230184-A
Country	US
Kind code	B2
Filing date	Sep 12, 2011
Priority date	Sep 13, 2010
Publication date	May 26, 2015
Grant date	May 26, 2015

Abstract

In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured.

First claim

The invention claimed is:

1. A memory device comprising:
a driver circuit; and
a plurality of memory cell arrays which is provided over the driver circuit and is configured to be driven by the driver circuit,
wherein each of the plurality of memory cell arrays comprises a plurality of memory cells arranged in matrix,
wherein each of the plurality of memory cells comprises a first transistor comprising a channel formation region in an oxide semiconductor layer,
wherein the driver circuit comprises a second transistor comprising a channel formation region comprising a semiconductor material other than an oxide semiconductor,
wherein the second transistor is provided below the first transistor with an insulating layer provided therebetween, and
wherein the plurality of memory cell arrays is stacked to overlap.

2. The memory device according to claim 1 ,
wherein each of the plurality of memory cell arrays comprises a bit line which is electrically connected to one of a source electrode and a drain electrode of the first transistor, and
wherein the bit lines of the plurality of memory cell arrays are electrically connected to each other.

3. The memory device according to claim 1 ,
wherein each of the plurality of memory cell arrays comprises a word line which is electrically connected to a first gate electrode of the first transistor, and
wherein the word lines of the plurality of memory cell arrays are electrically connected to each other.

4. The memory device according to claim 2 , wherein the bit lines of at least two adjacent memory cell arrays of the plurality of memory cell arrays are arranged so as not to overlap with each other.

5. The memory device according to claim 3 , wherein the word lines of at least two adjacent memory cell arrays of the plurality of memory cell arrays are arranged so as not to overlap with each other.

6. The memory device according to claim 1 ,
wherein the channel formation region of the second transistor is provided in a substrate comprising the semiconductor material other than the oxide semiconductor.

7. The memory device according to claim 1 ,
wherein the channel formation region of the second transistor is provided in a semiconductor layer comprising the semiconductor material other than the oxide semiconductor, the semiconductor layer being provided over an insulating surface.

8. The memory device according to claim 6 , wherein the semiconductor material other than the oxide semiconductor is silicon.

9. The memory device according to claim 7 , wherein the semiconductor material other than the oxide semiconductor is silicon.

10. The memory device according to claim 1 ,
wherein the driver circuit comprises a bit line driver circuit for driving bit lines and a word line driver circuit for driving word lines,
wherein the bit line driver circuit comprises a first driver circuit and a second driver circuit,
wherein the word line driver circuit comprises a third driver circuit and a fourth driver circuit, and
wherein the first to fourth driver circuits are arranged so as to be symmetrical with respect to a center point of one of the plurality of memory cell arrays.

11. A memory device comprising:
a driver circuit; and
a plurality of memory cell arrays which is provided over the driver circuit and is configured to be driven by the driver circuit,
wherein each of the plurality of memory cell arrays comprises a plurality of memory cells arranged in matrix,
wherein each of the plurality of memory cells comprises:
a first transistor comprising:
an oxide semiconductor layer;
a source electrode and a drain electrode;
a first gate insulating layer; and
a first gate electrode overlapping with the oxide semiconductor layer with the first gate insulating layer provided therebetween; and

a capacitor comprising:
one of the source electrode and the drain electrode;
an insulating layer in contact with the oxide semiconductor layer; and
a conductive layer overlapping with the one of the source electrode and the drain electrode with the insulating layer provided therebetween, and

wherein the plurality of memory cell arrays is stacked to overlap.

12. The memory device according to claim 11 ,
wherein each of the plurality of memory cell arrays comprises a bit line which is electrically connected to the other of the source electrode and the drain electrode of the first transistor, and
wherein the bit lines of the plurality of memory cell arrays are electrically connected to each other.

13. The memory device according to claim 11 ,
wherein each of the plurality of memory cell arrays comprises a word line which is electrically connected to the first gate electrode of the first transistor, and
wherein the word lines of the plurality of memory cell arrays are electrically connected to each other.

14. The memory device according to claim 12 , wherein the bit lines of at least two adjacent memory cell arrays of the plurality of memory cell arrays are arranged so as not to overlap with each other.

15. The memory device according to claim 13 , wherein the word lines of at least two adjacent memory cell arrays of the plurality of memory cell arrays are arranged so as not to overlap with each other.

16. The memory device according to claim 11 ,
wherein the driver circuit comprises a second transistor, and
wherein the second transistor comprises:
a channel formation region provided in a substrate comprising a semiconductor material other than an oxide semiconductor;
a pair of impurity regions with the channel formation region provided therebetween;
a second gate insulating layer over the channel formation region; and
a second gate electrode provided over the second gate insulating layer so as to overlap with the channel formation region.

17. The memory device according to claim 11 ,
wherein the driver circuit comprises a second transistor, and
wherein the second transistor comprises:
a channel formation region provided in a semiconductor layer comprising a semiconductor material other than an oxide semiconductor, the semiconductor layer being provided over an insulating surface;
a pair of impurity regions with the channel formation region provided therebetween;
a second gate insulating layer overlapping with the channel formation region; and
a second gate electrode provided so as to overlap with the channel formation region with the second gate insulating layer provided therebetween.

18. The memory device according to claim 16 , wherein the semiconductor material other than the oxide semiconductor is silicon.

19. The memory device according to claim 17 , wherein the semiconductor material other than the oxide semiconductor is silicon.

20. The memory device according to claim 11 ,
wherein the driver circuit comprises a bit line driver circuit for driving bit lines and a word line driver circuit for driving word lines,
wherein the bit line driver circuit comprises a first driver circuit and a second driver circuit,
wherein the word line driver circuit comprises a third driver circuit and a fourth driver circuit, and
wherein the first to fourth driver circuits are arranged so as to be symmetrical with respect to a center point of one of the plurality of memory cell arrays.

21. A memory device comprising:
a driver circuit; and
a plurality of memory cell arrays which is provided over the driver circuit and is configured to be driven by the driver circuit,
wherein each of the plurality of memory cell arrays compr

Assignees

• Koyama Jun
• Yamazaki Shunpei
• Semiconductor Energy Lab

Inventors

• Koyama Jun
• Yamazaki Shunpei

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/407 Primary

  for memory cells of the field-effect type · CPC title

• G11C11/404 Primary

  with one charge-transfer gate, e.g. MOS transistor, per cell · CPC title

• H10B12/20

  DRAM devices comprising floating-body transistors, e.g. floating-body cells · CPC title