Method for processing a semiconductor device with two closely spaced gates
US-2021391526-A1 · Dec 16, 2021 · US
Multi-band topological nanowires
US9040959B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9040959-B2 |
| Application number | US-201313860246-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 10, 2013 |
| Priority date | May 8, 2012 |
| Publication date | May 26, 2015 |
| Grant date | May 26, 2015 |
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Abstract
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A topological qubit wire hosts Majorana zero-energy modes and includes a superconductor, which may be an s-wave superconductor, and a quasi-1D nanowire, which may be a semi-conductor. The Majorana zero-energy modes are localized at ends of the quasi-1D nanowire, which may be sized and shaped to provide occupancy of a few transverse modes in a first direction and occupancy of a few transverse modes in a second direction. In some instances, the occupancy in the first direction may be greater than or equal to 3, and the occupancy in the second direction may be 1.
First claim
Opening claim text (preview).
What is claimed is: 1. A topological qubit wire, comprising: a superconductor; and a quasi-1D multi-band nanowire coupled, via quantum tunneling, to the superconductor and having a Majorana segment that supports Majorana zero-energy modes at opposed longitudinal ends of the Majorana segment, wherein the Majorana segment has a longitudinal length extending between the opposed longitudinal ends and a transverse width, and wherein the quantum tunneling between the superconductor an…
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Classifications
- H01L39/221Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10N60/11Primary
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9040959B2 cover?
- A topological qubit wire hosts Majorana zero-energy modes and includes a superconductor, which may be an s-wave superconductor, and a quasi-1D nanowire, which may be a semi-conductor. The Majorana zero-energy modes are localized at ends of the quasi-1D nanowire, which may be sized and shaped to provide occupancy of a few transverse modes in a first direction and occupancy of a few transverse mo…
- Who is the assignee on this patent?
- Microsoft Corp, Microsoft Technology Licensing Llc
- What technology area does this patent fall under?
- Primary CPC classification H01L39/221. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 26 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).