Manufacturing method for semiconductor structure
US-12165910-B2 · Dec 10, 2024 · US
Methods for fabricating integrated circuits having gate to active and gate to gate interconnects
US9040403B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9040403-B2 |
| Application number | US-201414244611-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 3, 2014 |
| Priority date | Sep 20, 2011 |
| Publication date | May 26, 2015 |
| Grant date | May 26, 2015 |
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- Title
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Abstract
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Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of fabricating an integrated circuit, the method comprising: forming a dummy gate structure comprising a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode; forming a contact on the semiconductor substrate adjacent the first sidewall spacer; removing the dummy gate electrode to form a trench bounded by the first and second sidewall space…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W10/014Primary
Electricity · mapped topic
- H10D64/017Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9040403B2 cover?
- Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bou…
- Who is the assignee on this patent?
- Globalfoundries Inc, Globalfoundries Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W10/014. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 26 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).