Semiconductor memory device and manufacturing method of semiconductor memory device
US-2024313073-A1 · Sep 19, 2024 · US
Method for processing a carrier, method for fabricating a charge storage memory cell, method for processing a chip, and method for electrically contacting a spacer structure
US9040375B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9040375-B2 |
| Application number | US-201313751185-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 28, 2013 |
| Priority date | Jan 28, 2013 |
| Publication date | May 26, 2015 |
| Grant date | May 26, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for processing a carrier, the method comprising: forming a structure over the carrier, the structure comprising two adjacent structure elements respectively formed in a U-shape so that the two adjacent structure elements are arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer is deposited having a thickness greater than half of the first distance, wherein the spacer layer comprises…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
- H10D64/037Primary
Electricity · mapped topic
Electricity · mapped topic
- H10D30/6891Primary
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9040375B2 cover?
- A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spac…
- Who is the assignee on this patent?
- Infineon Technologies Dresden Gmbh
- What technology area does this patent fall under?
- Primary CPC classification H10D64/037. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 26 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).