Structure to reduce chip shift during assembly
US-2024395758-A1 · Nov 28, 2024 · US
Film-assist molded gel-fill cavity package with overflow reservoir
US9040352B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9040352-B2 |
| Application number | US-201213535438-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 28, 2012 |
| Priority date | Jun 28, 2012 |
| Publication date | May 26, 2015 |
| Grant date | May 26, 2015 |
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Abstract
Official abstract text for this publication.
A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with film-assisted molding, a gel reservoir feature is formed so that gel used to protect components in the cavity does not come in contact with a lid covering the cavity or the junction between the lid and the package attachment region. The gel reservoir is used in conjunction with a formed level setting feature that controls the height of gel in the cavity. Benefits include decreased volume of the cavity, thereby decreasing an amount of gel-fill needed and thus reducing production cost of the package.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: providing a second semiconductor device embodied within a packaged semiconductor device assembly, wherein the second semiconductor device comprises a first and second major surface; forming an encapsulated region over the second major surface of the second semiconductor device using an encapsulant; forming a cavity region in the encapsulant over a first portion of the second major surface of the second semiconductor device using a fi…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9040352B2 cover?
- A semiconductor device package having a cavity formed using film-assisted molding techniques is provided. Through the use of such techniques the cavity can be formed in specific locations in the molded package, such as on top of a device die mounted on the package substrate or a lead frame. In order to overcome cavity wall angular limitations introduced by conformability issues associated with …
- Who is the assignee on this patent?
- Kuo Shun Meen, Li Li, Freescale Semiconductor Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W76/47. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 26 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).