Apparatus and method for determining the number of execution cores to keep active in a processor

Patent metadata

Field	Value
Publication number	US-9037889-B2
Application number	US-201213631679-A
Country	US
Kind code	B2
Filing date	Sep 28, 2012
Priority date	Sep 28, 2012
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.

First claim

The invention claimed is:

1. A processor, comprising:
a plurality of execution cores;
power management circuitry to dynamically determine a number of said execution cores that, when active, will cause said processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with said number of cores is higher as compared to any other number of active execution cores within an established power envelope.

2. The processor of claim 1 wherein said execution cores are within a graphics processor.

3. The processor of claim 2 wherein said processor comprises general purpose processing cores.

4. The processor of claim 1 wherein said power management circuitry accepts one or more static and dynamic input variables.

5. The processor of claim 4 wherein said one or more static input variables include any of:
a switching capacitance term to determine dynamic power consumption;
a reference current term to determine leakage power consumption;
a set of manufacturing related parameters to help determine how reference leakage and switching capacitance scale with temperature and voltage.

6. The processor of claim 4 wherein said one or more dynamic input variables include any of:
supply voltage;
temperature;
activity level of an execution core.

7. A processor, comprising:
a plurality of execution cores;
power management circuitry to determine a number of said execution cores to enable for operation by determining:
a set of configurations of said processor that remain within a power envelope established for said processor, each configuration corresponding to a different number of active execution cores;
a change in power consumption as function of change in frequency parameter for each of said configurations within said set of configurations;
a configuration from said set of configurations having a lowest change in power consumption as a function of change in frequency parameter from amongst the other configurations of said said set.

8. The processor of claim 7 wherein said execution cores are within a graphics processor.

9. The processor of claim 8 wherein said processor comprises general purpose processing cores.

10. The processor of claim 7 wherein said power management circuitry accepts one or more static and dynamic input variables.

11. The processor of claim 10 wherein said one or more static input variables include any of:
a switching capacitance term to determine dynamic power consumption;
a reference current term to determine leakage power consumption;
a set of manufacturing related parameters to help determine how reference leakage and switching capacitance scale with temperature and voltage.

12. The processor of claim 10 wherein said one or more dynamic input variables include any of:
supply voltage;
temperature;
activity level of an execution core.

13. A method, comprising:
determining a set of configurations of a processor that remain within a power envelope established for said processor, each configuration corresponding to a different number of active execution cores of said processor;
determining a change in power consumption as function of change in frequency parameter for each of said configurations within said set of configurations; and,
determining a configuration from said set of configurations having a lowest change in power consumption as a function of change in frequency parameter from amongst the other configurations of said set.

14. The method of claim 13 wherein said configuration corresponds to a number of active execution cores that causes said processor to operate with a higher gain in performance as a function of power consumption than any other number of active execution cores for a region that said processor is operating within.

15. The method of claim 13 wherein said execution cores are within a graphics processor.

16. The method of claim 13 wherein said execution cores are general purpose processing cores within a multi-core processor.

17. The method of claim 13 further comprising accepting one or more static and dynamic input variables.

18. The method of claim 17 wherein said one or more static input variables include any of:
a switching capacitance term to determine dynamic power consumption;
a reference current term to determine leakage power consumption; and
a set of manufacturing related parameters to help determine how reference leakage and switching capacitance scale with temperature and voltage.

19. The method of claim 17 wherein said one or more dynamic input variables include any of:
supply voltage;
temperature;
activity level of an execution core.

20. A machine readable storage medium, that is not a signal, containing stored program code that when processed by a digital processing system causes a method to be performed, comprising:
determining a set of configurations of a processor that remain within a power envelope established for said processor, each configuration corresponding to a different number of active execution cores of said processor;
determining a change in power consumption as function of change in frequency parameter for each of said configurations within said set of configurations; and,
determining a configuration from said set of configurations having a lowest change in power consumption as a function of change in frequency parameter from amongst the other configurations of said set.

Assignees

• Ananthakrishnan Avinash N
• Sebot Julien Fefe
• Schwartz Jay D
• Gunther Stephen H
• Samson Eric C
• Intel Corp

Inventors

• Ananthakrishnan Avinash N
• Sebot Julien Fefe
• Schwartz Jay D
• Gunther Stephen H
• Samson Eric C

Classifications

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/324

  by lowering clock frequency · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3293 Primary

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title