Low speed access to DRAM

Patent metadata

Field	Value
Publication number	US-9036718-B2
Application number	US-201314132703-A
Country	US
Kind code	B2
Filing date	Dec 18, 2013
Priority date	Jun 30, 2005
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver.

First claim

What is claimed is:

1. An apparatus, comprising:
a memory array to store data;
an output multiplexer to provide data to a read path;
a serializer, coupled to the memory array and the output multiplexer, to receive data from the memory array, and provide data received from the memory array to the output multiplexer at a first speed; and
an out of band access circuitry, coupled to the memory array and the output multiplexer, in parallel with the serializer, to receive data fro…

Assignees

• Intel Corp

Inventors

• Zimmerman David J
• Williams Michael W

Classifications

• G11C5/066 Primary

  Physics · mapped topic

• G11C7/109

  Physics · mapped topic

• G06F13/28 Primary

  Physics · mapped topic

• G11C7/10

  Physics · mapped topic

• G11C11/4076

  Physics · mapped topic