System control using sparse data
US-12072810-B2 · Aug 27, 2024 · US
US9036403B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9036403-B2 |
| Application number | US-201213718967-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 18, 2012 |
| Priority date | Aug 20, 2012 |
| Publication date | May 19, 2015 |
| Grant date | May 19, 2015 |
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The semiconductor memory device includes a cell capacitor having a first terminal electrically connected to a storage node and a second terminal electrically connected to an internal node, an internal voltage generator configured to generate an internal voltage signal applied to the internal node in response to a power-up signal, and an initialization element configured to initialize the internal node in response to the power-up signal.
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What is claimed is: 1. A semiconductor memory device comprising: a cell capacitor having a first terminal electrically connected to a storage node and a second terminal electrically connected to a first internal node; a first internal voltage generator configured to generate a first internal voltage signal applied to the first internal node in response to a power-up signal; a second internal voltage generator configured to generate a second internal voltage signal applied to a…
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