Resistive memory array and method for controlling operations of the same

Patent metadata

Field	Value
Publication number	US-9036397-B2
Application number	US-201213624761-A
Country	US
Kind code	B2
Filing date	Sep 21, 2012
Priority date	Apr 2, 2010
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance. A resistive memory array including an array of the above resistive memory units, word lines and bit lines is also described, wherein the word (bit) lines are coupled to the first (second) memory layers.

First claim

What is claimed is:

1. A resistive memory array, comprising:
a plurality of resistive memory units arranged in rows and columns, wherein each of the resistive memory units comprises a first memory cell, and a second memory cell disposed under and electrically connected in series with the first memory cell, wherein each of the resistive memory units includes:
a first solid electrolyte, being a part of the first memory cell;
a second solid electrolyte, being a part of the second…

Assignees

• Macronix Int Co Ltd

Inventors

• Chien Wei-Chih
• Lee Ming-Hsiu
• Lee Feng-Ming

Classifications

• G11C11/5614

  Physics · mapped topic

• G11C11/5685

  Physics · mapped topic

• H01L45/1233

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic