Display device and driving method thereof

Patent metadata

Field	Value
Publication number	US-9035930-B2
Application number	US-201113067983-A
Country	US
Kind code	B2
Filing date	Jul 13, 2011
Priority date	Dec 3, 2010
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A display device may have a plurality of pixels of a first group connected to a plurality of first gate lines and first common voltage lines and a plurality of pixels of a second group connected to a plurality of second gate lines and second common voltage lines. The display device drives the first common voltage lines and the second common voltage lines in synchronization with a first clock signal; and drives the plurality of first gate lines and the plurality of second gate lines in synchronization with a second clock signal. I-th first and second common voltage lines (i is a positive integer) are driven to one of a first common voltage and a common reference voltage, and (i+1)-th first and second common voltage lines are driven to one of a second common voltage and the common reference voltage.

First claim

What is claimed is:

1. A display device, comprising:
a plurality of pixels of a first group and a plurality of pixels of a second group, wherein the plurality of pixels of the first group are connected to a plurality of first gate lines and first common voltage lines through which a common voltage of the pixels of the first group is supplied, and the plurality of pixels of the second group are connected to a plurality of second gate lines and second common voltage lines through which a common voltage of the pixels of the second group is supplied;
a first gate driver driving the plurality of first gate lines with a plurality of first gate driving signals, and outputting a plurality of first line enable signals which respectively correspond to the plurality of first common voltage lines;
a first common voltage driver receiving the plurality of first line enable signals and driving the first common voltage lines in response to the plurality of first line enable signals;
a second gate driver driving the plurality of second gate lines with a plurality of second gate driving signals, and outputting a plurality of second line enable signals which respectively correspond to second common voltage lines; and
a second common voltage driver receiving the plurality of second line enable signals and driving the second common voltage lines in response to the plurality of second line enable signals,
wherein driving the first common voltage lines is performed inversely by the first common voltage driver per frame, driving the second common voltage lines is performed inversely by the second common voltage driver per frame, and driving the first common voltage lines and the second common voltage lines are performed inversely, respectively, prior to driving corresponding first and second gate lines of the plurality of first and second gate lines with corresponding first and second gate driving signals of the plurality of first and second gate driving signals, respectively.

2. The display device as claimed in claim 1 , wherein the first gate driver includes a plurality of stages, and each stage of the plurality of stages drives the corresponding first gate line of the plurality of first gate lines, and outputs a corresponding first line enable signal of the plurality of first line enable signals.

3. The display device as claimed in claim 2 , wherein each stage of the plurality of stages includes:
a latch circuit latching a previous first line enable signal from a previous stage to output the corresponding first line enable signal, in response to a first clock signal; and
an output circuit driving the corresponding first gate line of the plurality of first gate lines according to the corresponding first line enable signal, in response to a second clock signal.

4. The display device as claimed in claim 3 , wherein the latch circuit includes:
a clock generator that, upon receiving the first clock signal, generates a first sub clock signal and a second sub clock signal;
a first switching device including an input terminal to receive the previous first line enable signal and an output terminal, and operating in response to the first clock signal and the first sub clock signal;
a NOR gate that, upon receiving a signal of the output terminal of the first switching device and a reset signal, outputs the corresponding first line enable signal; and
a second switching device connected between the corresponding first line enable signal and the output terminal of the first switching device, and operating in response to the first and the second sub clock signal.

5. The display device as claimed in claim 4 , wherein the output circuit includes:
a logic circuit receiving the second clock signal and the corresponding first line enable signal; and
a plurality of inverters serially and sequentially connected between an output terminal of the logic circuit and the corresponding first gate line of the plurality of first gate lines.

6. The display device as claimed in claim 3 , wherein the first common voltage driver includes a plurality of first common voltage units, and each first common voltage unit of the plurality of common voltage units drives a corresponding first common voltage line to one selected between a first common voltage and a common reference voltage in response to the corresponding first line enable signal.

7. The display device as claimed in claim 6 , wherein each first common voltage unit of the plurality of common voltage units includes:
a first inverter including an input terminal for receiving the corresponding first line enable signal, and an output terminal;
a second inverter including an input terminal connected to the output terminal of the first inverter, and an output terminal;
a first transistor connected between the first common voltage and the corresponding first common voltage line, and including a gate connected to the output terminal of the first inverter;
a second transistor connected between the first common voltage and the corresponding first common voltage line, and including a gate connected to the output terminal of the second inverter;
a third transistor connected between the common reference voltage and the corresponding first common voltage line, and including a gate connected to the output terminal of the first inverter; and
a fourth transistor connected between the common reference voltage and the corresponding first common voltage line, and including a gate connected to the output terminal of the second inverter.

8. The display device as claimed in claim 6 , wherein the second common voltage driver includes a plurality of second common voltage units, and each second common voltage unit of the plurality of common voltage units drives a corresponding second common voltage line of the second common voltage lines to one selected between a second common voltage and the common reference voltage in response to the corresponding second line enable signal.

9. The display device as claimed in claim 8 , wherein the first common voltages and the second common voltages have complementary voltage levels, and are inverted per frame.

10. The display device as claimed in claim 8 , wherein:
an i-th first common voltage line (where i is a positive integer) is driven to the first common voltage,
an (i+1)-th first common voltage line is driven to the second common voltage, and
an interval in which the i-th first common voltage line is driven to the first common voltage partially overlaps with an interval in which the (i+1)-th first common voltage line is driven to the second common voltage.

11. The display device as claimed in claim 1 , wherein the first gate driver includes a plurality of stages, and each stage of the plurality of stages drives the corresponding first gate line of the plurality of first gate lines, and outputs at least two corresponding first line enable signals corresponding to the corresponding first common voltage line of the plurality of first common voltage lines.

12. The display device as claimed in claim 11 , wherein each stage of the plurality of stages includes:
a first transistor connected between a gate line corresponding to a previous stage and a first node, and including a gate controlled by a first driving signal;
a second transistor connected between a gate line corresponding to a next stage and the first node, and including a gate controlled by a second driving signal;
a third transistor connected between the first node and a third node, and including a gate controlled by a first clock signal;
a fourth transistor connected between a first bias voltage and a second node, and including a gate connected to the first node;
a fifth tran

Assignees

• Lee Seung Kyu
• Park Jinwoo
• Lee Dong-Hoon
• Samsung Display Co Ltd

Inventors

• Lee Seung Kyu
• Park Jinwoo
• Lee Dong-Hoon

Classifications

• G11C19/184

  with field-effect transistors, e.g. MOS-FET · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2300/0434

  Flat panel display in which a field is applied parallel to the display plane · CPC title

• G09G2300/0876

  Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title