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US-11929108-B2 · Mar 12, 2024 · US
Method of in-process intralayer yield detection, interlayer shunt detection and correction
US9035673B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9035673-B2 |
| Application number | US-69301910-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 25, 2010 |
| Priority date | Jan 25, 2010 |
| Publication date | May 19, 2015 |
| Grant date | May 19, 2015 |
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Abstract
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A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
First claim
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What is claimed is: 1. A method for in-process yield evaluation in an array type of device, comprising: measuring an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical property to identify interlayer shunt defects; wherein interlayer shunt defects are identified through a process including: measuring electrical resistance between individual DATA lines and the GATE bus I/O…
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Electricity · mapped topic
Electricity · mapped topic
Physics · mapped topic
Physics · mapped topic
- G11C29/025Primary
Physics · mapped topic
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- What does patent US9035673B2 cover?
- A system and method for in-process yield evaluation and correction in an array type of device are provided. The system and method include measuring electrical resistance between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance to identify at least one of the following: GATE line open defects, GATE line bridge defects…
- Who is the assignee on this patent?
- Young Michael Yu Tak, Limb Scott Jong Ho, Wong William S, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G11C29/025. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue May 19 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).