Method of making metal substrates with structures formed therein
US-2024404922-A1 · Dec 5, 2024 · US
Semiconductor device
US9035472B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9035472-B2 |
| Application number | US-201314081585-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 15, 2013 |
| Priority date | Nov 16, 2012 |
| Publication date | May 19, 2015 |
| Grant date | May 19, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has conductor apertures. The outlines of the apertures and the conductor apertures overlap with each other, in a plan view, respectively.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a semiconductor chip having a front surface over which a plurality of electrode pads is formed, and a back surface opposite to the front surface; and a wiring board having a chip mounting surface over which the semiconductor chip is mounted, a mounting surface opposite to the chip mounting surface, a plurality of first pads arranged over the chip mounting surface and electrically connected with the electrode pads of the s…
Assignees
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9035472B2 cover?
- In a semiconductor device, a conductor pattern is disposed in a position overlapped by a semiconductor chip in a thickness direction over the mounting surface (lower surface) of a wiring board. A solder resist film (insulating layer) covering the lower surface of the wiring board has apertures formed such that multiple portions of the conductor pattern are exposed. The conductor pattern has con…
- Who is the assignee on this patent?
- Renesas Electronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W40/228. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 19 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).