Wiring board and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9035463-B2
Application number	US-201313895834-A
Country	US
Kind code	B2
Filing date	May 16, 2013
Priority date	May 18, 2012
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A wiring board includes a first insulation layer, a first conducive layer having first conductive patterns formed on the first insulation layer, a wiring structure positioned on the first insulation layer and including a second insulation layer and a second conductive layer having second conductive patterns formed on the second insulation layer, multiple conductive patterns formed on the wiring structures such that the conductive patterns are connected to the second conductive patterns, respectively, multiple first electrodes formed on the first conductive patterns, respectively, and multiple second electrodes formed on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively. The first electrodes and the second electrodes have top surfaces which form the same plane.

First claim

What is claimed is:

1. A wiring board, comprising:
a first insulation layer;
a first conductive layer comprising a plurality of first conductive patterns formed on the first insulation layer;
a wiring structure positioned on the first insulation layer and comprising a second insulation layer and a second conductive layer comprising a plurality of second conductive patterns formed on the second insulation layer;
a plurality of conductive patterns formed on the wiring structure such that the conductive patterns are connected to the second conductive patterns, respectively;
a plurality of first electrodes formed on the plurality of first conductive patterns, respectively; and
a plurality of second electrodes formed on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively,
wherein the first electrodes and the second electrodes have top surfaces which form a same plane.

2. The wiring board according to claim 1 , wherein the plurality of second conductive patterns has a pattern width which is set smaller than a pattern width of the plurality of first conductive patterns.

3. The wiring board according to claim 1 , wherein the plurality of second conductive patterns has an adjacent distance between the second conductive patterns which is set smaller than an adjacent distance between the first conductive patterns.

4. The wiring board according to claim 2 , wherein the plurality of second conductive patterns has an adjacent distance between the second conductive patterns which is set smaller than an adjacent distance between the first conductive patterns.

5. The wiring board according to claim 1 , further comprising a solder-resist layer formed on the first insulation layer such that the solder-resist layer is formed on the first conductive layer, the wiring structure and the conductive patterns formed on the second conductive patterns, wherein the solder-resist layer has a plurality of opening portions exposing at least portions of the first conductive patterns, respectively, and a plurality of opening portions exposing at least portions of the conductive patterns connected to the second conductive patterns, respectively.

6. The wiring board according to claim 1 , wherein the wiring structure includes a third insulation layer covering the second conductive patterns and a plurality of via structures connected to the plurality of second conductive patterns, respectively.

7. The wiring board according to claim 6 , further comprising an adhesive layer interposed between the first insulation layer and the wiring structure.

8. The wiring board according to claim 1 , further comprising:
a plurality of first mounting pads formed on the plurality of first conductive patterns, respectively, such that the plurality of first mounting pads is positioned to mount a first semiconductor device; and
a plurality of second mounting pads formed on the conductive patterns connected to the second conductive patterns, respectively, such that the plurality of second mounting pads is positioned to mount a second semiconductor device.

9. The wiring board according to claim 8 , wherein the plurality of first pads and the plurality of second pads are formed such that the first pads are distanced at a pitch which is set smaller than a pitch distancing the second pads.

10. The wiring board according to claim 1 , wherein the plurality of second conductive patterns forms a signal line positioned to be connected to a first semiconductor device and a second semiconductor device.

11. The wiring board according to claim 1 , wherein the plurality of second conductive patterns has a L/S which is set in a range of from 1 μm/1 μm to 5 μm/5 μm.

12. The wiring board according to claim 1 , wherein the first insulation layer has an opening portion accommodating the wiring structure.

13. A method for manufacturing a wiring board, comprising:
forming a first conductive layer comprising a plurality of first conductive patterns on a first insulation layer;
positioning on the first insulation layer a wiring structure comprising a second insulation layer and a second conductive layer comprising a plurality of second conductive patterns formed on the second insulation layer;
forming a plurality of conductive patterns on the second conductive patterns such that the conductive patterns are connected to the second conductive patterns, respectively;
forming a plurality of first electrodes on the plurality of first conductive patterns, respectively; and
forming a plurality of second electrodes on the conductive patterns connected to the second conductive patterns of the wiring structure, respectively,
wherein the plurality of first electrodes and the plurality of second electrodes are formed such that the first electrodes and the second electrodes have top surfaces which form a same plane.

14. The method for manufacturing a wiring board according to claim 13 , further comprising:
forming a solder-resist layer on the first insulation layer such that the solder-resist layer is formed on the first conductive layer, the wiring structure and the conductive patterns formed on the second conductive patterns; and
forming in the solder-resist layer a plurality of opening portions exposing at least portions of the first conductive patterns, respectively, and a plurality of opening portions exposing at least portions of the conductive patterns connected to the second conductive patterns, respectively.

15. The method for manufacturing a wiring board according to claim 13 , further comprising forming an opening portion in the first insulation layer, wherein the positioning of the wiring structure includes placing the wiring structure in the opening portion of the first insulation layer.

16. The method for manufacturing a wiring board according to claim 13 , further comprising:
forming an opening portion in the first insulation layer; and
forming an adhesive layer on a portion of the first insulation layer in the opening portion of the first insulation layer,
wherein the positioning of the wiring structure includes placing the wiring structure on the adhesive layer in the opening portion of the first insulation layer.

Assignees

• Ibiden Co Ltd

Inventors

• Shizuno Yoshinori
• Takahashi Nobuya
• Nakagome Hisayuki
• Ii Asuka

Classifications

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/012

  of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills · CPC title