Transistors, methods of manufacturing the same, and electronic devices including transistors

Patent metadata

Field	Value
Publication number	US-9035294-B2
Application number	US-201213550752-A
Country	US
Kind code	B2
Filing date	Jul 17, 2012
Priority date	Dec 6, 2011
Publication date	May 19, 2015
Grant date	May 19, 2015

Abstract

A transistor may include a channel layer formed of an oxide semiconductor. The oxide semiconductor may include GaZnON, and a proportion of Ga content to a total content of Ga and Zn of the channel layer is about 0.5 to about 4.5 at %.

First claim

What is claimed is:

1. A transistor comprising:
a channel layer including GaZuON, wherein a proportion of Ga content to a total content of Ga and Zn of the channel layer is 1 at % to 3 at %;
a source and a drain configured to contact first and second regions of the channel layer, respectively;
a gate corresponding to the channel layer; and
a gate insulating layer between the channel layer and the gate.

2. The transistor of claim 1 , wherein the proportion of Ga content to the total content of Ga and Zn of the channel layer is 1.5 at % to 2.5 at %.

3. The transistor of claim 1 , wherein the Ga content of the channel layer is about 0.5 to about 1.5 at %.

4. The transistor of claim 1 , wherein the channel layer has a thickness of about 10 to about 150 nm.

5. The transistor of claim 1 , wherein the channel layer is on the gate.

6. The transistor of claim 5 , further comprising:
an etch stop layer on the channel layer.

7. The transistor of claim 1 , wherein the gate is on the channel layer.

8. A flat display apparatus comprising the transistor of claim 1 .

9. A method of manufacturing a transistor, the method comprising:
forming a gate;
forming a channel layer corresponding to the gate, the channel layer including GaZnON; and
forming a source and a drain contacting first and second regions of the channel layer, respectively,
wherein the channel layer is fat wed such that a proportion of Ga content to a total content of Ga and Zn is 1 at % to 3 at %.

10. The method of claim 9 , wherein the forming a channel layer includes forming the channel layer by a reactive sputtering method.

11. The method of claim 10 , wherein the forming a channel layer includes forming the channel layer using a Ga 2 O 3 target and a Zn target.

12. The method of claim 10 , wherein the forming a channel layer includes forming the channel layer using O 2 gas and N 2 gas as a reaction gas in the reactive sputtering method.

13. The method of claim 12 , wherein the forming the channel layer includes using the O 2 gas at a flow rate of about 1 to about 15 sccm, and the N 2 gas has a flow rate of about 20 to about 150 sccm.

14. The method of claim 12 , wherein the forming the channel layer includes forming the channel layer using argon (Ar) gas for generating plasma.

15. The method of claim 14 , wherein the forming the channel layer includes supplying the Ar gas at a flow rate of about 1 to about 50 sccm.

16. The method of claim 10 , wherein the forming the channel layer by a reactive sputtering method includes forming the channel layer at a temperature from room temperature to about 100° C.

17. The method of claim 9 , wherein the forming a channel layer includes forming the channel layer by a metal organic chemical vapor deposition (MOCVD) method.

18. The method of claim 9 , further comprising:
annealing the transistor at a temperature of about 250 to about 350° C.

19. The method of claim 9 , wherein the forming a channel layer includes forming the channel layer on the gate.

20. The method of claim 19 , further comprising:
foxing an etch stop layer on the channel layer.

21. The method of claim 9 , wherein the forming a gate includes forming the gate on the channel layer.

22. A channel layer comprising GaZnON, wherein a proportion of Ga content to a total content of Ga and Zn of the channel layer is 1 at % to 3 at %.

23. The channel layer of claim 22 , wherein the proportion of Ga content to the total content of Ga and Zn is 1.5 at % to 2.5 at %.

24. The channel layer of claim 22 , wherein the Ga content is about 0.5 to about 1.5 at %.

25. The channel layer of claim 22 , wherein the channel layer has a thickness of about 10 to about 150 nm.

26. The transistor of claim 1 , wherein a threshold voltage variation of the transistor is in a range of −0.79 V to −0.36 V.

27. The method of claim 9 , wherein a threshold voltage variation of the transistor is in a range of −0.79 V to −0.36 V.

28. The channel layer of claim 22 , wherein a threshold voltage variation of a transistor including the channel layer is in a range of −0.79 V to −0.36 V.

Assignees

• Park Joon-Seok
• Kim Tae-Sang
• Kim Hyun-Suk
• Ryu Myung-Kwan
• Seon Jong-Baek
• Son Kyoung-Seok
• Lee Sang-Yoon
• Seo Seok-Jun
• Samsung Display Co Ltd

Inventors

• Park Joon-Seok
• Kim Tae-Sang
• Kim Hyun-Suk
• Ryu Myung-Kwan
• Seon Jong-Baek
• Son Kyoung-Seok
• Lee Sang-Yoon
• Seo Seok-Jun

Classifications

• Y10T428/24479

  including variation in thickness · CPC title

• B32B3/26 Primary

  characterised by a particular shape of the outline of the cross-section of a continuous layer; characterised by a layer with cavities or internal voids {(foam layer B32B5/18; layer of synthetic resin characterised by fillers that create voids or cavities B32B27/205); characterised by an apertured layer} · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title