Semiconductor device fabrication method and semiconductor device

US9034708B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9034708-B2
Application numberUS-201314101373-A
CountryUS
Kind codeB2
Filing dateDec 10, 2013
Priority dateDec 21, 2012
Publication dateMay 19, 2015
Grant dateMay 19, 2015

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

There is provided a method of fabricating a semiconductor device, the method including: forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus; after the first etching, performing a second etching that etches the rear surface with an etching method with a lower etching rate than the first etching; and after the second etching, forming a second semiconductor region through which the current is to flow, by implanting impurities from the rear surface of the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a semiconductor device, the method comprising: forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the rear surface of the substrate with a chemical solution including phosphorus;…

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What does patent US9034708B2 cover?
There is provided a method of fabricating a semiconductor device, the method including: forming a first semiconductor region at a front surface of a substrate, the first semiconductor region including an active element that regulates current flowing in a thickness direction of the substrate; grinding a rear surface of the substrate; after the grinding, performing a first etching that etches the…
Who is the assignee on this patent?
Lapis Semiconductor Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D62/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 19 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).