Victim cache that supports draining write-miss entries
US-2024264952-A1 · Aug 8, 2024 · US
Memory arbitration system and method having an arbitration packet protocol
US9032166B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9032166-B2 |
| Application number | US-201314049109-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 8, 2013 |
| Priority date | Mar 24, 2004 |
| Publication date | May 12, 2015 |
| Grant date | May 12, 2015 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.
First claim
Opening claim text (preview).
What is claimed is: 1. An apparatus, comprising: a first memory hub coupled to a memory device, the first memory hub configured to, responsive to a read request, retrieve read data from the memory device based on the read request and generate arbitration data associated with the read request, wherein generation of the arbitration data at least partially overlaps with retrieval of the read data from the memory device, the first memory hub further configured to provide the arbitrati…
Assignees
Inventors
Classifications
- G06F13/1642Primary
Physics · mapped topic
Physics · mapped topic
- G06F13/1605Primary
Physics · mapped topic
- G06F13/16Primary
Physics · mapped topic
Patent family
Related publications grouped by family.
External sources
Next steps
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9032166B2 cover?
- A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data o…
- Who is the assignee on this patent?
- Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F13/1642. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue May 12 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).