Memory controller for memory with mixed cell array and method of controlling the memory

Patent metadata

Field	Value
Publication number	US-9032136-B2
Application number	US-201213610830-A
Country	US
Kind code	B2
Filing date	Sep 11, 2012
Priority date	Aug 17, 2012
Publication date	May 12, 2015
Grant date	May 12, 2015

Abstract

A memory controller, system including the memory controller and method of controlling the memory. The memory controller receives requests for memory and content sensitively allocates memory space in a mixed cell memory. The memory controller allocates sufficient space including performance memory storing a single bit per cell and dense memory storing more than one bit per cell. Some or all of the memory may be selectable by the memory controller as either Single Level per Cell (SLC) or Multiple Level per Cell (MLC).

First claim

What is claimed is:

1. A method of managing memory comprising:
receiving a request to allocate mixed cell memory from one of a plurality of processing units sharing said mixed cell memory, said mixed cell memory comprising performance memory and dense memory;
identifying performance requirements for content associated with said request; and
allocating said performance memory and dense memory, content sensitively responsive to identified said performance requirements associated…

Assignees

• Dai Bing
• Lam Chung H
• Li Jing
• IBM

Inventors

• Dai Bing
• Lam Chung H
• Li Jing

Classifications

• G06F12/0246 Primary

  Physics · mapped topic

• G06F1/32

  Physics · mapped topic

• G06F12/02 Primary

  Physics · mapped topic