Providing a load/store communication protocol with a low power physical unit

Patent metadata

Field	Value
Publication number	US-9031064-B2
Application number	US-201414186677-A
Country	US
Kind code	B2
Filing date	Feb 21, 2014
Priority date	May 22, 2012
Publication date	May 12, 2015
Grant date	May 12, 2015

Abstract

In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a logic to operate a Peripheral Component Interconnect Express™ (PCIe™)-based transaction layer and a link layer; and
a physical unit coupled to the logic to transmit and receive data via a physical link, the physical unit including a link training and status state machine (LTSSM), a M-PHY electrical layer, and a logical layer to interface the logic with the M-PHY electrical layer, wherein the LTSSM is to configure and initialize the physical link to a link width determined prior to training the physical link.

2. The apparatus of claim 1 , wherein the M-PHY electrical layer includes a plurality of physical unit circuits each to communicate via a single channel of the physical link.

3. The apparatus of claim 1 , wherein the LTSSM is to support multi-lane communications.

4. The apparatus of claim 1 , wherein the LTSSM is to support asymmetric link width configurations.

5. The apparatus of claim 1 , wherein the LTSSM is to support dynamic bandwidth scalability.

6. The apparatus of claim 1 , wherein the physical link has an asymmetric width from the apparatus to a device coupled to the apparatus via the physical link as from the device to the apparatus.

7. The apparatus of claim 6 , wherein the physical link is configurable to operate at an asymmetric frequency from the apparatus to the device as from the device to the apparatus.

8. The apparatus of claim 7 , further comprising a sideband interconnect coupled between the apparatus and the device.

9. The apparatus of claim 1 , wherein the physical link is to be configured for an initial link width and frequency from a reset of the apparatus.

10. The apparatus of claim 1 , wherein the apparatus comprises a system on chip (SoC) having a plurality of cores, the logic coupled to the plurality of cores.

11. The apparatus of claim 8 , wherein the apparatus further comprises a second physical unit to enable communication with the device via the sideband interconnect.

12. The apparatus of claim 8 , wherein the apparatus is to send first information via the physical link at a first data rate and to send second information via the sideband interconnect at a second data rate, the second data rate less than the first data rate.

13. A system comprising:
a system on a chip (SoC) including:
a plurality of cores;
a transaction layer and a link layer according to a Peripheral Component Interconnect Express™ (PCIe™) communication protocol; and
a physical unit coupled to the link layer to enable communication via a physical link, the physical unit comprising an electrical layer not of the PCIe™ communication protocol and a logical layer to interface the link layer to the electrical layer, the physical unit including a link training and management state machine (LTSSM), wherein the LTSSM is to configure and initialize the physical link to a link width determined prior to training the physical link;

the physical link coupled between the SoC and a first transceiver, wherein the physical link is configurable to operate with an asymmetric width from the SoC to the first transceiver as from the first transceiver to the SoC;
the first transceiver coupled to the SoC via the physical link, the first transceiver including:
a second transaction layer and a second link layer according to the PCIe™communication protocol; and
a second physical unit coupled to the second link layer to enable communication via the physical link, the second physical unit comprising a second electrical layer not of the PCIe™ communication protocol and a second logical layer to interface the second link layer with the second electrical layer;

an image capture device coupled to the SoC to capture image information; and
a touchscreen display coupled to the SoC.

14. The system of claim 13 , wherein the physical unit includes a plurality of physical unit circuits each to communicate via a single channel of the physical link.

15. The system of claim 13 , wherein the LTSSM is to support dynamic bandwidth scalability.

16. The system of claim 13 , wherein the system comprises a tablet computer.

17. A method comprising:
determining a link width for a physical link that couples a root complex and a device prior to a training process for the physical link, wherein the root complex includes a logic to operate a Peripheral Component Interconnect Express™ (PCIe™)-based transaction layer and a link layer, and a physical unit coupled to the protocol stack to provide communication between the root complex and the device, the physical unit including a link training and management logic, a M-PHY electrical layer and a logical layer to interface the logic with the M-PHY electrical layer;
configuring and initializing the physical link to the determined link width; and
training the physical link, including performing a bit lock per lane of the physical link, performing a symbol lock per lane of the physical link, and performing lane-to-lane deskew for multiple lanes of the physical link.

18. The method of claim 17 , further comprising supporting one or more of multi-lane communications, asymmetric link width configurations, and dynamic bandwidth scalability via the link training and management logic.

19. The method of claim 17 , further comprising configuring a sideband interconnect coupled between the root complex and the device.

20. The method of claim 19 , further comprising sending first information via the physical link at a first data rate and sending second information via the sideband interconnect at a second data rate, the second data rate less than the first data rate.

Assignees

• Intel Corp

Inventors

• Ranganathan Sridharan
• Wagh Mahesh
• Harriman David J

Classifications

• H04L49/109 Primary

  Integrated on microchip, e.g. switch-on-chip · CPC title

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/40

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title