Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
US9030867B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9030867-B2 |
| Application number | US-50221109-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 13, 2009 |
| Priority date | Oct 20, 2008 |
| Publication date | May 12, 2015 |
| Grant date | May 12, 2015 |
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A resistive sense memory apparatus includes a bipolar select device having a semiconductor substrate and a plurality of transistors disposed in the semiconductor substrate and forming a row or transistors. Each transistor includes an emitter contact and a collector contact. Each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other. A gate contact extends along a channel region between the emitter contact and a collector contact. A base contact is disposed within the semiconductor substrate such that the emitter contact and a collector contact is between the gate contact and the base contact. A resistive sense memory cells is electrically coupled to each collector contact or emitter contact and a bit line.
Opening claim text (preview).
What is claimed is: 1. A resistive sense memory apparatus comprising: a bipolar select device comprising: a semiconductor substrate; a plurality of field effect transistors disposed in the semiconductor substrate and forming a row of field effect transistors, each field effect transistor comprising an emitter contact and a collector contact, wherein each collector contact is electrically isolated from each other and each emitter contact is electrically isolated from each other,…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Physics · mapped topic
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