Electro-optic apparatus and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9030616-B2
Application number	US-201213572869-A
Country	US
Kind code	B2
Filing date	Aug 13, 2012
Priority date	Aug 17, 2011
Publication date	May 12, 2015
Grant date	May 12, 2015

Abstract

A retention capacity in which a first electrode, a lower side capacity insulation film, a second electrode, an upper side capacity insulation film, and a third electrode are laminated is formed between a pixel electrode and a TFT. The lower side capacity insulation film and the upper side capacity insulation film respectively include a plurality of insulation films, and the lamination order thereof is the same.

First claim

What is claimed is:

1. An electro-optic apparatus, comprising:
a pixel electrode which is provided for each pixel;
a transistor which is provided to correspond to each pixel electrode; and
a capacitor which is provided between the pixel electrode and the transistor, the capacitor including
a first electrode, a second electrode arranged to face a transistor side of the first electrode, a first insulation film provided between the first electrode and the second electrode, a second insulation film provided between the first electrode and the first insulation film, a third electrode arranged to face a pixel electrode side of the first electrode, a third insulation film provided between the first electrode and the third electrode, and a fourth insulation film provided between the third electrode and the third insulation film,

wherein,
the first insulation film and the third insulation film include a silicon oxide,
the second insulation film and the fourth insulation film include a silicon nitride,
the second electrode and the third electrode are electrically connected via a relay wiring, and
a lamination order of the first insulation film including the silicon oxide and the second insulation film including the silicon nitride arranged on the transistor side of the first electrode, and a lamination order of the third insulation film including the silicon oxide and the fourth insulation film including the silicon nitride arranged on the pixel electrode side of the first electrode, are asymmetrical about the first electrode.

2. The electro-optic apparatus according to claim 1 ,
wherein a predetermined constant potential is supplied to the first electrode, and
wherein the second electrode and the third electrode are electrically connected to the pixel electrode and the transistor, respectively.

3. The electro-optic apparatus according to claim 1 ,
wherein the first electrode is electrically connected to the pixel electrode and the transistor, and
wherein a predetermined constant potential is supplied to each of the second electrode and the third electrode.

4. An electronic apparatus comprising the electro-optic apparatus according to claim 1 .

5. The electro-optic apparatus according to claim 1 , wherein
the first insulation film abuts the second electrode;
the second insulation film abuts the first electrode;
the third insulation film abuts the first electrode; and
the fourth insulation film abuts the third electrode.

6. The electro-optic apparatus according to claim 5 , wherein
the second insulation film abuts the first electrode on a side of the first electrode facing the transistor; and
the third insulation film abuts the first electrode on a side of the first electrode facing the pixel electrode.

7. An electro-optic apparatus, comprising:
a pixel electrode;
a transistor that is electrically connected to the pixel electrode; and
a capacitor that is electrically connected to the pixel electrode, the capacitor including a first electrode, a second electrode, a third electrode, a first insulation film that is disposed between the first electrode and the second electrode, a second insulation film that is disposed between the first electrode and the first insulation film, a third insulation film that is disposed between the first electrode and the third electrode, and a fourth insulation film that is disposed between the third electrode and the third insulation film,
wherein,
the first insulation film and the third insulation film include a silicon oxide,
the second insulation film and the fourth insulation film include a silicon nitride
the second electrode and the third electrode are electrically connected via a relay wiring, and
a lamination order of the first insulation film including the silicon oxide and the second insulation film including the silicon nitride arranged on the transistor side of the first electrode, and a lamination order of the third insulation film including the silicon oxide and the fourth insulation film including the silicon nitride arranged on the pixel electrode side of the first electrode, are asymmetrical about the first electrode.

8. The electro-optic apparatus according to claim 7 ,
wherein the first electrode is electrically connected to the pixel electrode.

9. The electro-optic apparatus according to claim 7 ,
wherein the relay wiring is electrically connected to a capacitor wiring.

10. The electro-optic apparatus according to claim 1 ,
wherein the relay wiring extends through a contact hole in one or more layers on which the first electrode and at least one of the second electrode and the third electrode are formed.

11. The electro-optic apparatus according to claim 1 ,
wherein the second electrode is electrically connected to the transistor, the third electrode is electrically connected to the pixel electrode, and a predetermined constant potential is supplied to the first electrode.

12. The electro-optic apparatus according to claim 7 ,
wherein the relay wiring extends through a contact hole in one or more layers on which the first electrode and at least one of the second electrode and the third electrode are formed.

13. The electro-optic apparatus according to claim 7 ,
wherein the second electrode is electrically connected to the transistor, the third electrode is electrically connected to the pixel electrode, and a predetermined constant potential is supplied to the first electrode.

Assignees

• Moriwaki Minoru
• Seiko Epson Corp

Inventors

• Moriwaki Minoru

Classifications

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/136213

  Storage capacitors associated with the pixel electrode · CPC title

• G02F1/136277 Primary

  formed on a semiconductor substrate, e.g. of silicon · CPC title