System and methods for generating unclonable security keys in integrated circuits

Patent metadata

Field	Value
Publication number	US-9030226-B2
Application number	US-201314076541-A
Country	US
Kind code	B2
Filing date	Nov 11, 2013
Priority date	Jan 12, 2010
Publication date	May 12, 2015
Grant date	May 12, 2015

Abstract

A system and methods that generates a physical unclonable function (“PUF”) security key for an integrated circuit (“IC”) through use of equivalent resistance variations in the power distribution system (“PDS”) to mitigate the vulnerability of security keys to threats including cloning, misappropriation and unauthorized use.

First claim

What is claimed is:

1. A security key generating system for an integrated circuit, comprising:
one or more stimulus-measure circuit;
an operational amplifier;
a first voltage sense wire;
a second voltage sense wire, wherein said first voltage sense wire and said second voltage sense wire are each electrically connected to said one or more stimulus-measure circuit and to said operational amplifier, said operational amplifier configured to output a logic value in order to generate a security key, the logic value determined by a comparison of a first voltage on said first voltage sense wire and a second voltage on said second voltage sense wire.

2. The system of claim 1 , wherein the logic value is a first value when the first voltage on said first voltage sense wire is larger than the second voltage on said second voltage sense wire.

3. The system of claim 1 , wherein the logic value is a second value when the first voltage on said first voltage sense wire is smaller than the second voltage on said second voltage sense wire.

4. The system of claim 1 , wherein the logic value is a bit response.

5. The system of claim 1 further comprising a key generation control unit, wherein said key generation control unit drives one or more signals of said one or more stimulus-measure circuit.

6. The system of claim 5 , wherein the one or more signals is a scan pattern selected from a group comprising: a scan-in signal, a scan-out signal, and a scan-clock signal.

7. The system of claim 1 , wherein said one or more stimulus-measure circuit further comprises one or more shorting inverters.

8. The system of claim 7 further comprising a key generation control unit, wherein said key generation control unit drives one or more signals of said one or more stimulus-measure circuit.

9. The system of claim 8 , wherein the one or more signals enable the one or more shorting inverters of said one or more stimulus-measure circuit.

10. The system of claim 1 further comprising a voltage sense transistor configured to measure a voltage of one or more of said first voltage sense wire and said second voltage sense wire.

11. The system of claim 1 further comprising a power grid connected to said one or more stimulus-measure circuit.

12. The system of claim 1 further comprising a ground grid connected to said one or more stimulus-measure circuit.

13. A method for generating a security key, comprising the steps of:
providing a substrate including one or more stimulus-measure circuit, an operational amplifier, a key generation control unit, a first voltage sense wire and a second voltage sense wire;
comparing a first voltage on the first voltage sense wire and a second voltage on the second voltage sense wire;
outputting by the operational amplifier a bit response depending on whether the first voltage on the first voltage sense wire is larger or smaller than the second voltage on the second voltage sense wire;
sending the bit response to the key generation control unit;
repeating said comparing step, said outputting step and said sending step to obtain two or more bit responses; and
generating a security key from the two or more bit responses.

14. The method of claim 13 , wherein substrate further includes a power grid connected to the one or more stimulus-measure circuit.

15. The method of claim 13 , wherein the substrate further includes a ground grid connected to the one or more stimulus-measure circuit.

16. The method of claim 13 , wherein the key generation control unit drives one or more signals of the one or more stimulus-measure circuit.

17. The method of claim 16 , wherein the one or more signals enable one or more shorting inverters of the one or more stimulus-measure circuit.

18. The method of claim 13 , wherein the one or more signals is a scan pattern selected from a group comprising: a scan-in signal, a scan-out signal, and a scan-clock signal.

19. The method of claim 13 further comprising a voltage sense transistor configured to measure the first voltage on the first voltage sense wire and the second voltage on the second voltage sense wire.

Assignees

• Plusquellic James
• Acharyya Dhruva J
• Helinski Ryan L
• Stc Unm

Inventors

• Plusquellic James
• Acharyya Dhruva J
• Helinski Ryan L

Classifications

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• Y10T29/49124

  On flat or curved insulated base, e.g., printed circuit, etc. · CPC title

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• H04L9/0861 Primary

  Generation of secret information including derivation or calculation of cryptographic keys or passwords · CPC title