Semiconductor wafer and method for auto-calibrating integrated circuit chips using PLL at wafer level

US9030217B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9030217-B2
Application numberUS-201213605554-A
CountryUS
Kind codeB2
Filing dateSep 6, 2012
Priority dateApr 23, 2012
Publication dateMay 12, 2015
Grant dateMay 12, 2015

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Abstract

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In integrated circuit chips that are used for RFID, a method of calibrating an operation frequency that is generated in an operation frequency generator and a semiconductor wafer including a calibration circuit are provided. The method of calibrating an operation frequency of integrated circuit chips includes: supplying DC power to the integrated circuit chips; selecting an integrated circuit chip to perform calibration of an operation frequency; receiving an operation frequency that is generated in the selected integrated circuit chip; calculating a difference between a phase of the operation frequency and a phase of a calibration target frequency; generating a frequency calibration value of the operation frequency using the phase difference; transmitting a control signal including the frequency calibration value to the integrated circuit chip; and releasing a selection of the integrated circuit chip in which calibration of the operation frequency is complete.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of auto-calibrating integrated circuit chips at a wafer level by calibrating an operation frequency of the integrated circuit chips, the method comprising: supplying DC power to the integrated circuit chips; selecting an integrated circuit chip on which to perform calibration of an operation frequency; receiving an operation frequency that is generated in the selected integrated circuit chip; calculating a difference between a phase of the ope…

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What does patent US9030217B2 cover?
In integrated circuit chips that are used for RFID, a method of calibrating an operation frequency that is generated in an operation frequency generator and a semiconductor wafer including a calibration circuit are provided. The method of calibrating an operation frequency of integrated circuit chips includes: supplying DC power to the integrated circuit chips; selecting an integrated circuit c…
Who is the assignee on this patent?
Kim Hyunseok, Choi Su Na, Lee Heyung Sub, and 2 more
What technology area does this patent fall under?
Primary CPC classification G06K19/0726. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 12 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).