Semiconductor package and semiconductor devices with the same

Patent metadata

Field	Value
Publication number	US-9029989-B2
Application number	US-201313969053-A
Country	US
Kind code	B2
Filing date	Aug 16, 2013
Priority date	Sep 24, 2012
Publication date	May 12, 2015
Grant date	May 12, 2015

Abstract

A semiconductor package includes a substrate, a ground circuit supported by the substrate, at least one semiconductor chip disposed on the substrate and a carbon-containing heat-dissipating part disposed on the substrate and electrically connected to the ground circuit. The heat-dissipating part may include carbon fibers and/or carbon cloth.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate;
a ground circuit supported by the substrate;
at least one semiconductor chip disposed on the substrate; and
a carbon-containing heat-dissipating part disposed on the substrate adjacent a periphery of and not overlapping the at least one semiconductor chip and electrically connected to the ground circuit.

2. The semiconductor package of claim 1 , wherein the heat-dissipating part comprises carbon fibers and/or carbon cloth.

3. The semiconductor package of claim 1 , further comprising a connection pattern disposed adjacent to the at least one semiconductor chip and configured to electrically connect the ground circuit to the heat-dissipating part.

4. The semiconductor package of claim 1 , wherein the heat-dissipating part has a top surface that is lower than or substantially coplanar with a top surface of the at least one semiconductor chip.

5. The semiconductor package of claim 1 , further comprising a molding part covering the heat-dissipating part.

6. The semiconductor package of claim 1 , further comprising a molding part disposed on the substrate and covering the semiconductor chip and the heat-dissipating part.

7. The semiconductor package of claim 1 , wherein the heat-dissipating part comprises a first heat-dissipating part disposed adjacent a periphery of the semiconductor chip and wherein the package further comprises a second heat-dissipating part overlying the semiconductor chip and the first heat-dissipating pattern and electrically connected to the first heat-dissipating part via a pattern disposed between the first and second heat-dissipating patterns.

8. The semiconductor package of claim 7 , wherein the second heat-dissipating part comprise a metal and/or graphite.

9. The semiconductor package of claim 1 , wherein the at least one semiconductor chip comprises a plurality of semiconductor chips stacked on the substrate.

10. A semiconductor device, comprising:
a first semiconductor package comprising a first substrate, at least one first semiconductor chip disposed on the first substrate and a ground circuit supported by the first substrate;
a second package disposed on the first package and comprising a second substrate, at least one second semiconductor chip disposed on the second substrate, and a carbon-containing heat-dissipating part disposed on the substrate; and
a connecting part connecting the heat-dissipating part of the second package to the ground circuit of the first package.

11. The device of claim 10 , wherein the second package further comprises a molding part disposed on the second substrate and covering the heat-dissipating part.

12. The device of claim 10 , wherein the heat-dissipating part is disposed along a periphery of the at least one second semiconductor chip and has a top surface that is lower than or substantially coplanar with a top surface of the at least one second semiconductor chip.

13. The device of claim 10 , wherein the heat-dissipating part comprises a first heat-dissipating part disposed along a periphery of the at least one second semiconductor chip and wherein the device further includes a second heat-dissipating part electrically connected to the first heat-dissipating part and comprising metal and/or graphite.

14. A packaged semiconductor device comprising:
a substrate;
a ground circuit supported by the substrate;
at least one semiconductor chip disposed on the substrate;
a molded region disposed on the substrate and conforming to at least one sidewall of the at least one semiconductor chip; and
a carbon-containing region disposed in the molded region adjacent a periphery of the at least one semiconductor chip and connected to the ground circuit.

15. The packaged semiconductor device of claim 14 , wherein the carbon-containing region is thermally and electrically conductive.

16. The packaged semiconductor device of claim 14 , wherein the molded region at least partially covers a top surface of the at least one semiconductor chip.

17. The packaged semiconductor device of claim 14 , further comprising a metal and/or graphite region overlying the at least one semiconductor chip and connected to the carbon-containing region.

18. The packaged semiconductor device of claim 14 , wherein the carbon-containing region comprises carbon fibers and/or carbon cloth.

19. The semiconductor package of claim 1 , wherein the heat dissipating part comprises a rectangular pattern extending completely around the periphery of the at least one semiconductor chip.

Assignees

• Park Soojeoung
• Samsung Electronics Co Ltd

Inventors

• Park Soojeoung

Classifications

• H10W42/263

  Shielding bumps · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title