Optoelectronic device comprising microwires or nanowires
US-2015340552-A1 · Nov 26, 2015 · US
Separating semiconductor devices from substrate by etching graded composition release layer disposed between semiconductor devices and substrate including forming protuberances that reduce stiction
US9029239B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9029239-B2 |
| Application number | US-201314067433-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 30, 2013 |
| Priority date | Nov 1, 2007 |
| Publication date | May 12, 2015 |
| Grant date | May 12, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between each of the semiconductor devices and the substrate. The etch is stopped while the protuberances remain between each of the semiconductor devices and the substrate. The method also includes separating the semiconductor devices from the substrate. Other methods and apparatus are also disclosed.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch, including: etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate; and etching protuberances in the release layer such that a protuberance is etched between each of the semiconductor devices and the substrate;…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10F10/163Primary
Electricity · mapped topic
- H10F71/00Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9029239B2 cover?
- A method includes etching a release layer that is coupled between a plurality of semiconductor devices and a substrate with an etch. The etching includes etching the release layer between the semiconductor devices and the substrate until the semiconductor devices are at least substantially released from the substrate. The etching also includes etching a protuberance in the release layer between…
- Who is the assignee on this patent?
- Sandia Corp
- What technology area does this patent fall under?
- Primary CPC classification H10F10/163. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 12 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).