High throughput heated ion implantation system and method
US-2015380285-A1 · Dec 31, 2015 · US
Substrate processing apparatus and method of manufacturing semiconductor device
US9028191B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9028191-B2 |
| Application number | US-201113163165-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 17, 2011 |
| Priority date | Jun 17, 2010 |
| Publication date | May 12, 2015 |
| Grant date | May 12, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
Reduction in cooling rate of a substrate having a lower temperature is suppressed because the substrate having a lower temperature is not affected by radiant heat of a substrate having a higher temperature while cooling a plurality of substrates in a cooling chamber. The substrate processing apparatus includes a load lock chamber configured to accommodate stacked substrates; a first transfer mechanism having a first transfer arm provided with a first end effector, and configured to transfer the substrates into/from the load lock chamber at a first side of the load lock chamber; a second transfer mechanism having a second transfer arm provided with a second end effector, and configured to transfer the substrates into/from the load lock chamber at a second side of the load lock chamber; a barrier installed between the substrates to be spaced apart from the substrates supported by a substrate support provided in the load lock chamber; and an auxiliary barrier unit installed between the substrate support and the barrier, wherein the auxiliary barrier unit is installed at places other than standby spaces of the end effectors.
First claim
Opening claim text (preview).
What is claimed is: 1. A substrate processing apparatus comprising: a load lock chamber configured to accommodate a substrate support supporting stacked substrates including at least a first substrate and a second substrate; a first transfer mechanism having a first transfer arm provided with a first end effector having two fingers at a front end thereof, and configured to transfer the stacked substrates into/from the load lock chamber at a first side of the load lock chamber;…
Assignees
Inventors
Classifications
- H10P72/0466Primary
Electricity · mapped topic
- H10P72/0464Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9028191B2 cover?
- Reduction in cooling rate of a substrate having a lower temperature is suppressed because the substrate having a lower temperature is not affected by radiant heat of a substrate having a higher temperature while cooling a plurality of substrates in a cooling chamber. The substrate processing apparatus includes a load lock chamber configured to accommodate stacked substrates; a first transfer me…
- Who is the assignee on this patent?
- Yasui Takeshi, Hirochi Yukitomo, Takano Satoshi, and 3 more
- What technology area does this patent fall under?
- Primary CPC classification H10P72/0466. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 12 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).