Manufacturing method for photomask, and photomask
US-2024427229-A1 · Dec 26, 2024 · US
Compression method and system for use with multi-patterning
US9026953B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9026953-B2 |
| Application number | US-201314064229-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 28, 2013 |
| Priority date | Jul 12, 2012 |
| Publication date | May 5, 2015 |
| Grant date | May 5, 2015 |
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Abstract
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A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.
First claim
Opening claim text (preview).
What is claimed is: 1. A method comprising: providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of a single IC by multipatterning using at least two photomasks to pattern the single layer of the IC, such that first circuit patterns to be formed by the first mask and second circuit patterns to be formed by the second mask are added to form the IC layout including the first circuit patterns and…
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Frequently asked questions
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- What does patent US9026953B2 cover?
- A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group …
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G03F1/70. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue May 05 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).