Core test method and core test circuit
US-2024345941-A1 · Oct 17, 2024 · US
US9026401B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9026401-B2 |
| Application number | US-63667309-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 11, 2009 |
| Priority date | Dec 11, 2009 |
| Publication date | May 5, 2015 |
| Grant date | May 5, 2015 |
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Monitoring parameters of memory modules is described. According to certain embodiments, one or more parameters on respective memory modules are monitored. Corresponding parameter information is transmitted away from the respective memory module to a device that is external to the respective memory modules.
Opening claim text (preview).
What is claimed is: 1. A method comprising: monitoring one or more parameters on at least one respective memory module using an electronic apparatus that includes a differential pair of transistors configuration coupled between a power supply and ground potential and coupled to an output node, the differential pair of transistors configuration being housed on the respective memory module and wherein the differential pair of transistors configuration is operable to provide at the o…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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