Data write circuit of semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-9025397-B2
Application number	US-201313846723-A
Country	US
Kind code	B2
Filing date	Mar 18, 2013
Priority date	Dec 24, 2012
Publication date	May 5, 2015
Grant date	May 5, 2015

Abstract

A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to receive the pattern signal and generate a second delayed pattern signal; a data latch block configured to latch the first delayed pattern signal in response to the second delayed pattern signal, and output a resultant signal; and a control block configured to generate the pattern signal, and vary a delay time of the data path according to a result of comparing phases of a latched signal of the data latch block and the pattern signal.

First claim

What is claimed is:

1. A data write circuit of a semiconductor apparatus, comprising:
a data path;
a data strobe signal path; and
a control block configured to vary a delay time of the data path according to a phase difference between a signal having passed through the data path and a signal having passed through the data strobe signal path.

2. The data write circuit according to claim 1 , further comprising:
a data latch block configured to latch the s…

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Il

Classifications

• G11C7/1093

  Physics · mapped topic

• G11C7/1012 Primary

  Physics · mapped topic

• G11C7/1087

  Physics · mapped topic

• G11C7/22

  Physics · mapped topic

• G11C7/1096

  Physics · mapped topic