Demand-paged textures

Patent metadata

Field	Value
Publication number	US-9024959-B2
Application number	US-64291709-A
Country	US
Kind code	B2
Filing date	Dec 21, 2009
Priority date	Dec 21, 2009
Publication date	May 5, 2015
Grant date	May 5, 2015

Abstract

A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image.

First claim

We claim:

1. A method comprising:
reserving at runtime virtual address space for a virtual image corresponding to a texture image;
binding the virtual address space as data a texture sampler reads when rendering, wherein the virtual address space is not backed by physical memory;
issuing a texture sampling request for a texel of the virtual image to the texture sampler that makes a read from a portion of the virtual image using a first virtual address of the reserved virtual a…

Assignees

• Duprat Jean-Luc
• Lalonde Paul
• Forsyth Andrew T
• Intel Corp

Inventors

• Duprat Jean-Luc
• Lalonde Paul
• Forsyth Andrew T

Classifications

• G06T11/10 Primary

  Physics · mapped topic

• H04N19/60

  Electricity · mapped topic

• G06T9/00

  Physics · mapped topic

• G06T15/04

  Physics · mapped topic

• G06T11/001 Primary

  Physics · mapped topic