System and method for controlling circuit input-output timing

US9024670B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9024670-B2
Application numberUS-201314048238-A
CountryUS
Kind codeB2
Filing dateOct 8, 2013
Priority dateOct 8, 2013
Publication dateMay 5, 2015
Grant dateMay 5, 2015

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Abstract

Official abstract text for this publication.

An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a control register associated with each of the I/O terminals, a memory, and I/O delay control logic. The control register is coupled to each of the delay elements associated with the I/O terminal. The memory is encoded with delay information. The I/O delay control logic is configured to initialize the propagation delay associated with each of the I/O terminals by selecting which of the delay elements are to be applied to produce the propagation delay based on the delay information stored in the memory.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit (IC), comprising: a plurality of input/output (I/O) terminals through which signals pass into or out of the IC; and an I/O timing module configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC, the I/O timing module comprising: a plurality of delay elements associated with each of the I/O terminals; a control register associated with each of the I/O terminals and coupled to each…

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What does patent US9024670B2 cover?
An integrated circuit (IC) includes a plurality of input/output (I/O) terminals through which signals pass into or out of the IC and an I/O timing module. The I/O timing module is configured to add propagation delay to signals passing between the I/O terminals and I/O subsystems of the IC. The I/O timing module includes a plurality of delay elements associated with each of the I/O terminals, a …
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H03K5/159. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 05 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).