Energy augmentation structures, energy emitters or energy collectors containing the same, and their use in solar cells and other energy conversion devices
US-2024115878-A1 · Apr 11, 2024 · US
Field-effect P-N junction
US9024367B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9024367-B2 |
| Application number | US-201313773985-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 22, 2013 |
| Priority date | Feb 24, 2012 |
| Publication date | May 5, 2015 |
| Grant date | May 5, 2015 |
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Abstract
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This disclosure provides systems, methods, and apparatus related to field-effect p-n junctions. In one aspect, a device includes an ohmic contact, a semiconductor layer disposed on the ohmic contact, at least one rectifying contact disposed on the semiconductor layer, a gate including a layer disposed on the at least one rectifying contact and the semiconductor layer and a gate contact disposed on the layer. A lateral width of the rectifying contact is less than a semiconductor depletion width of the semiconductor layer. The gate contact is electrically connected to the ohmic contact to create a self-gating feedback loop that is configured to maintain a gate electric field of the gate.
First claim
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What is claimed is: 1. A device comprising: a semiconductor layer, a thickness of the semiconductor layer being comparable to a semiconductor depletion width of the semiconductor layer; an ohmic contact disposed on a first side of the semiconductor layer; a rectifying contact disposed on the first side the semiconductor layer, the rectifying contact being electrically isolated from the ohmic contact; and a gate including a layer disposed on a second side of the semiconductor…
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Frequently asked questions
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- What does patent US9024367B2 cover?
- This disclosure provides systems, methods, and apparatus related to field-effect p-n junctions. In one aspect, a device includes an ohmic contact, a semiconductor layer disposed on the ohmic contact, at least one rectifying contact disposed on the semiconductor layer, a gate including a layer disposed on the at least one rectifying contact and the semiconductor layer and a gate contact disposed…
- Who is the assignee on this patent?
- Univ California
- What technology area does this patent fall under?
- Primary CPC classification H10F10/10. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 05 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).